Dual-Channel Nanosheet Transistor Structure for Short-Channel Suppression
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Solution Overview
Problem
Current semiconductor devices face challenges in improving gate controllability and suppressing the short channel effect, especially as devices become more highly integrated.
Innovation Solution
The semiconductor device employs a dual-channel nano sheet transistor structure, where silicon nano sheets and silicon germanium nano sheets are vertically stacked with isolation walls in between, and gates are formed to cover at least three surfaces of the nano sheets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional planar transistors are used, then manufacturing is simple, but gate controllability deteriorates and short channel effect increases
Solution Approach 1:
The patent transitions from two-dimensional planar channels to three-dimensional vertically stacked nano sheet channels. Multiple thin nano sheets are stacked in the vertical direction to form a channel structure that provides superior gate controllability while maintaining compatibility with existing manufacturing processes.
Solution Approach 2:
The channel is divided into multiple thin nano sheet segments stacked vertically. Each nano sheet is a thin semiconductor layer (e.g., silicon or SiGe) that is segmented from the bulk material, allowing independent control and optimized electrical characteristics for each layer while collectively providing enhanced performance.
2Productivity
If channel length is reduced to increase integration density, then productivity improves, but short channel effect worsens
Solution Approach 1:
By stacking multiple nano sheets vertically, the patent achieves higher integration density in the vertical dimension while maintaining adequate horizontal channel length. This three-dimensional approach allows continued scaling without suffering from short channel effects that plague planar transistors with reduced channel lengths.
Solution Approach 2:
The patent employs composite material structures including alternating layers of different semiconductor materials (e.g., silicon and SiGe) with different bandgaps. This composite structure enables selective etching to form suspended nano sheets with enhanced electrical characteristics and reduced short channel effects.
Data Source
AI summary
A semiconductor device comprises: a substrate including first and second buried source/drain layers; a first nano sheet stack including first nano sheets stacked in a direction vertical to the substrate; a second nano sheet stack including second nano sheets stacked in a direction vertical to the substrate; an isolation wall disposed between the first nano sheet stack and the second nano sheet stack; first gate covering portions of the first nano sheet stack and extending in a direction vertical to the substrate; second gate covering portions of the second nano sheet stack and extending in a direction vertical to the substrate; first common source/drain layers connected to end portions of the first nano sheets and to the first buried source/drain layers; and second common source/drain layers connected to end portions of the second nano sheets and to the second buried source/drain layers.