Dual-Channel Semiconductor Assembly for Heat and Vertical Current Flow

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Solution Overview

Problem

Existing ceramic-based semiconductor assemblies struggle to effectively dissipate heat and facilitate vertical electricity transmission due to limitations in thermal conductivity and the difficulty in forming large-size vertically connecting elements, making them unsuitable for high power applications.

Innovation Solution

A semiconductor assembly with dual conduction channels is designed, featuring a top substrate and a base substrate with electrode connection plates and slugs, along with routing circuitries, to provide high current flow and efficient heat flux dissipation, utilizing materials with high thermal and electrical conductivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Stability of the object's composition

If ceramic materials are used for semiconductor chip interconnect base, then CTE matching is improved, but thermal conductivity and electrical conductivity are worsened

Engineering Contradiction:
ImproveCTE matchingVSAvoidheat dissipation
Core Design Contradiction:
Stability of the object's compositionVSTemperature

Solution Approach 1:

The interconnect base is segmented into multiple functional layers: a ceramic substrate layer for CTE matching, a thermally conductive layer for heat dissipation, and an electrically conductive layer for current flow. This segmentation allows each layer to optimize its specific function without compromising the others.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention uses a composite structure combining ceramic materials with thermally conductive and electrically conductive materials. The ceramic substrate provides mechanical stability and CTE matching, while the additional layers provide enhanced thermal and electrical conductivity, creating a multi-functional composite interconnect base.

Inventive Principle:
Principle #40Composite materials

2Stability of the object's composition

If ceramic materials are used for semiconductor chip interconnect base, then CTE matching is improved, but electrical conductivity for vertical current transmission is worsened

Engineering Contradiction:
ImproveCTE matchingVSAvoidvertical electricity transmission
Core Design Contradiction:
Stability of the object's compositionVSReliability

Solution Approach 1:

The interconnect base is segmented into multiple functional layers: a ceramic substrate layer for CTE matching, a thermally conductive layer for heat dissipation, and an electrically conductive layer for current flow. This segmentation allows each layer to optimize its specific function without compromising the others.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention uses a composite structure combining ceramic materials with thermally conductive and electrically conductive materials. The ceramic substrate provides mechanical stability and CTE matching, while the additional layers provide enhanced thermal and electrical conductivity, creating a multi-functional composite interconnect base.

Inventive Principle:
Principle #40Composite materials

3Reliability

If large-size vertically connecting elements are formed in ceramic, then electrical conductivity is improved, but manufacturing complexity increases

Engineering Contradiction:
Improvevertical electricity transmissionVSAvoidforming vertically connecting elements
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The interconnect base is segmented into multiple functional layers: a ceramic substrate layer for CTE matching, a thermally conductive layer for heat dissipation, and an electrically conductive layer for current flow. This segmentation allows each layer to optimize its specific function without compromising the others.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the interconnect base have different properties optimized for their specific functions. The ceramic substrate provides mechanical stability, while the electrically conductive layer provides high conductivity paths. This local optimization allows large-size vertically connecting elements to be formed in the conductive layer without compromising the overall structural integrity provided by the ceramic.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The assembly achieves improved thermal and electrical performance by ensuring high current flow and effective heat dissipation, suitable for high power applications.

Implementation Method 1

The electrode connection plate and the electrode connection slug can offer high current flow channels and also ensure high heat flux dissipation for the semiconductor device

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Implementation Method 2

The electrode connection plate and the electrode connection slug can offer high current flow channels

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentUS12575434B2Semiconductor assembly having dual conduction channels for electricity and heat passage
Publication Date: 2026.03.10 BRIDGE SEMICON CORP
  • US12575434B2 patent drawing
  • US12575434B2 patent drawing
  • US12575434B2 patent drawing

AI summary

A semiconductor assembly includes a top substrate and a base substrate attached to top and bottom electrode layers of a semiconductor device, respectively. The top substrate includes an electrode connection plate thermally conductible with and electrically connected to the top electrode layer of the semiconductor device and vertical posts protruding from the electrode connection plate and electrically connected to the base substrate. The base substrate includes an electrode connection slug embedded in a dielectric layer and thermally conductible with and electrically connected to the bottom electrode layer of the semiconductor device and first and second routing circuitries deposited on two opposite surfaces of the dielectric layer, respectively, and electrically connected to each other.