Dual-Channel Transistor 3D Memory Structure
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Solution Overview
Problem
The fabrication of 3D memory structures, particularly 3D DRAM memory cells, is complex and costly due to the need for three material layers of distinct etch selectivity, which complicates the processing and is challenging to implement effectively.
Innovation Solution
A 3D memory structure using dual-channel thin-film transistors with a dual-channel gate driven by a wordline and abutting a horizontal capacitor, along with a simplified fabrication process employing two material layers of distinct etch selectivity, reduces contact resistance and enhances read/write speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If three material layers of distinct etch selectivity are used in 3D memory structure fabrication, then manufacturing precision can be improved, but device complexity and fabrication cost increase significantly
Solution Approach 1:
The patent extracts and eliminates the requirement for three distinct material layers with different etch selectivities. By redesigning the fabrication process to use only two material layers, the patent removes the complexity associated with managing three different materials while maintaining the necessary etch selectivity through alternative means, thus resolving the contradiction between manufacturing precision and device complexity
Solution Approach 2:
The patent changes the material layer parameter from three distinct layers to two layers. This parameter change reduces fabrication complexity while maintaining etch selectivity through the strategic selection and arrangement of the two remaining material layers, thereby resolving the technical contradiction
2Device complexity
If conventional single-channel transistors are used in 3D memory structures, then device complexity is reduced, but contact resistance increases and read/write speeds decrease
Solution Approach 1:
The patent segments the transistor channel into multiple parallel channels (dual-channel architecture) within the same transistor structure. This segmentation provides multiple conduction paths, reducing contact resistance and improving read/write speeds without significantly increasing overall device complexity, as the segmented channels share common structures
Solution Approach 2:
The patent transitions from a conventional planar single-channel transistor to a dual-channel transistor that utilizes vertical stacking and three-dimensional positioning. By adding the vertical dimension to the channel architecture, the patent achieves lower contact resistance through improved contact geometry while maintaining manageable device complexity
Data Source
AI summary
A memory structure includes a spacer between a first side of a wordline conductor and a bitline conductor. A semiconductor material has horizontal portions extending from the bitline conductor along a top and bottom of the wordline conductor and has a contact portion extending along a second side of the wordline conductor between and connecting the horizontal portions. A high-κ dielectric is between the semiconductor material and the wordline conductor. A capacitor has a first conductor, a second conductor, and an insulator between the first and second conductors, where the first conductor contacts the contact portion of the semiconductor material along the first side of the wordline conductor, and the second conductor connects to a ground terminal.