Dual-Channel Variable-Granularity Memory Access for Lower Energy Retrieval

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Solution Overview

Problem

Existing memory systems face inefficiencies in data access due to coarse granularity, leading to significant energy consumption and wasteful data retrieval when accessing small, dispersed data units.

Innovation Solution

Implementing a dual-channel memory component with variable access granularity, allowing transition between volume-mode and resolution-mode operations, where resolution-mode reduces data access granularity by a factor of four, using sub-row and sub-column addressing, and optionally merging memory banks for peak throughput.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If coarse granularity memory access is used, then data throughput is maintained, but energy consumption increases and data retrieval efficiency decreases

Engineering Contradiction:
Improveenergy consumptionVSAvoiddata retrieval efficiency
Core Design Contradiction:
Use of energy by moving objectVSProductivity

Solution Approach 1:

The memory system segments data access into two distinct modes: volume-mode for bulk data transfer and resolution-mode for fine-grained access. This segmentation allows the system to optimize for either throughput or efficiency depending on the access pattern, resolving the contradiction between energy consumption and retrieval efficiency.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The memory system dynamically transitions between volume-mode and resolution-mode operations based on access requirements. The dual-channel architecture enables flexible switching between coarse and fine granularity, allowing the system to adapt to different workload characteristics and optimize both energy efficiency and productivity.

Inventive Principle:
Principle #15Dynamics

2Loss of energy

If fine granularity data access is implemented, then energy efficiency improves, but data throughput decreases

Engineering Contradiction:
Improveenergy efficiencyVSAvoiddata throughput
Core Design Contradiction:
Loss of energyVSProductivity

Solution Approach 1:

The memory access system is segmented into two operational modes with distinct characteristics. Volume-mode provides coarse-grained access optimized for high throughput, while resolution-mode provides fine-grained access optimized for energy efficiency. This segmentation eliminates the need to choose one mode permanently, allowing optimal performance for different access patterns.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The memory system achieves multi-functionality by incorporating both volume-mode and resolution-mode capabilities within a single architecture. The dual-channel design with separate decode logic for each mode enables the system to perform both bulk data transfer and fine-grained access operations, making it universally applicable to diverse workload requirements.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Adaptability or versatility

If dual-channel memory architecture is used, then access flexibility improves, but device complexity increases

Engineering Contradiction:
Improveaccess flexibilityVSAvoiddevice complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The dual-channel architecture segments the memory control logic into separate pathes for volume-mode and resolution-mode operations. Each channel has dedicated decode logic tailored to its specific access pattern, which simplifies the control complexity within each channel while providing overall system flexibility. The segmented design avoids the need for complex mode-switching logic within a single channel.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20250244918A1Variable memory access granularity
Publication Date: 2025.07.31 RAMBUS INC
  • US20250244918A1 patent drawing
  • US20250244918A1 patent drawing
  • US20250244918A1 patent drawing

AI summary

An integrated-circuit memory component receives, as part of respective first and second memory read transactions, a first column access command that identifies a first volume of data and a second column read command that identifies a second volume of data, the second volume of data being constituted by not more than half as many data bits as the first volume of data. In response to receiving the first column access command, the integrated-circuit memory component transmits the first volume of data as N parallel bit-serial data signals over N external signaling links. In response to receiving the second column access command, the integrated-circuit memory component transmits the second volume of data as M parallel bit-serial data signals over M of the N external signaling links, where M is less than N.