Dual Charge Storage Nodes with Dielectric Plug
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Solution Overview
Problem
As semiconductor memory devices shrink in size, the reduced spacing between dual charge storage nodes leads to reliability and retention issues due to charge leakage and programming disturbances, as well as bit line punch through, limiting erasing options.
Innovation Solution
A dual charge storage node memory device is fabricated with physically split charge storage nodes, using a dielectric plug to separate the nodes and prevent bit line punch through, and a control gate is formed over the nodes to enable Fowler-Nordheim tunneling for erasing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device size is reduced to increase storage capacity, then memory capacity increases, but charge leakage between storage nodes increases
Solution Approach 1:
The charge storage layer is divided into two separate segments, one for each storage node, with a dielectric plug physically separating them. This segmentation prevents charge leakage between nodes while maintaining high storage capacity in reduced device size.
Solution Approach 2:
A dielectric plug is introduced as an intermediary structure between the two charge storage nodes. This mediator physically isolates the nodes, preventing charge migration while allowing the device to maintain high capacity in a compact form factor.
2Productivity
If spacing between storage nodes is reduced to increase density, then device density increases, but programming disturbance to other nodes increases
Solution Approach 1:
The charge storage layer is segmented into separate regions for each node, with the dielectric plug creating physical boundaries. This allows high device density through reduced spacing while preventing programming disturbances from affecting adjacent nodes.
Solution Approach 2:
The harmful interaction between nodes is eliminated by extracting the charge storage function into separate, isolated regions. Each node's charge storage is taken out and placed in its own isolated compartment, preventing cross-node disturbances while maintaining high density.
3Productivity
If spacing between bit lines is reduced to increase density, then device density increases, but punch through between bit lines occurs
Solution Approach 1:
The dielectric plug serves as an intermediary barrier between bit lines, physically separating them and preventing punch through effects. This allows the device to achieve high density through reduced bit line spacing while maintaining electrical isolation.
Solution Approach 2:
The harmful punch through effect is eliminated by extracting the bit lines into separate, isolated regions defined by the dielectric plug. Each bit line is taken out and placed in its own isolated channel, preventing harmful interactions while maintaining high device density.
4Device complexity
If single continuous charge storage layer is used to simplify structure, then manufacturing complexity decreases, but charge leakage between nodes increases
Solution Approach 1:
The charge storage layer is segmented into separate sections for each node, with the dielectric plug creating physical boundaries. This segmentation maintains relatively simple manufacturing processes while ensuring reliable charge isolation between nodes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents charge leakage and programming disturbances, maintains data integrity, and allows reliable erasing by physically isolating charge storage nodes and using a dielectric plug to block bit line punch through, enhancing memory device reliability and capacity.
Implementation Method 1
a first charge storage node and a second charge storage node separated by a dielectric plug
Implementation Method 2
allows erasing by Fowler-Nordheim tunneling
Implementation Method 3
Ions are implanted into the substrate to form a first bit line and second bit line
Data Source
AI summary
A dual charge storage node memory device and methods for its fabrication are provided. In one embodiment a dielectric plug is formed comprising a first portion recessed into a semiconductor substrate and a second portion extending above the substrate. A layer of semiconductor material is formed overlying the second portion. A first layered structure is formed overlying a first side of the second portion of the dielectric plug, and a second layered structure is formed overlying a second side, each of the layered structures overlying the layer of semiconductor material and comprising a charge storage layer between first and second dielectric layers. Ions are implanted into the substrate to form a first bit line and second bit line, and a layer of conductive material is deposited and patterned to form a control gate overlying the dielectric plug and the first and second layered structures.