Dual-Chip Lead Frame Package for Higher TVS Power Density
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing lead frame packages for transient voltage suppression (TVS) diodes typically support only a single semiconductor chip, limiting power density and flexibility in device combinations, and do not efficiently utilize dual inline package (DIP) configurations.
Innovation Solution
A two-in-one lead frame package design that supports two semiconductor devices within a single package, using high-temperature attachment material (HTAM) and low-temperature attachment material (LTAM) to secure chips and clips, allowing for various semiconductor combinations and DIP-type lead frames, enhancing power density and flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single chip is supported in the lead frame package, then the device complexity is reduced and manufacturing is simplified, but the power density and flexibility are limited
Solution Approach 1:
The package structure is segmented into distinct functional zones: a first chip mounting area, a second chip mounting area, and a common lead frame base. This segmentation allows independent mounting of different chip types in each area while maintaining a unified package structure, enabling flexible device combinations without proportionally increasing overall complexity
Solution Approach 2:
The lead frame package is designed with universal mounting structures that can accommodate multiple types of semiconductor chips simultaneously. The common lead frame base and standardized die attachment pads provide multi-functional support for different chip configurations, allowing the same package to serve multiple application scenarios
2Power
If a single chip is mounted in the package, then the attachment process is simpler and faster, but the power density is limited
Solution Approach 1:
The patent merges multiple chip mounting operations into a single integrated package assembly process. By combining the first chip, second chip, and lead frame into one unified package structure with common attachment points, the design enables simultaneous mounting of multiple chips without requiring separate assembly steps for each chip, thereby increasing power density while maintaining assembly efficiency
Solution Approach 2:
The package design utilizes vertical stacking or dual-side mounting arrangements, transitioning from a single-plane chip mounting approach to a multi-dimensional configuration. This allows two chips to be mounted in the same package footprint by utilizing different spatial dimensions, effectively doubling the power density without proportionally increasing the assembly area or time
3Reliability
If standard DIP configurations are used, then the manufacturing process is well-established and reliable, but the utilization efficiency and performance are suboptimal
Solution Approach 1:
While maintaining the overall DIP package form factor for manufacturing compatibility, the invention implements local quality variations in the internal structure. The lead frame is designed with differentiated zones: a first die attachment pad area optimized for one chip type and a second die attachment pad area optimized for another chip type. This local customization within the standardized package enables performance optimization for specific device combinations while preserving the reliability of established DIP manufacturing processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The two-in-one design increases power density by supporting two semiconductor devices, allows for flexible combinations of semiconductor products, and enables a two-channel design, improving the overall performance and versatility of transient voltage suppression devices.
Implementation Method 1
A high-temperature attachment material (HTAM) is dispensed onto a first side of a die attachment pad of a lead frame package. A first chip is attached to the first side, and the HTAM affixes the first chip to the die attachment pad.
Implementation Method 2
The HTAM is dispensed onto the first chip. The HTAM is dispensed onto a first lead portion and the first clip is attached between the first chip and the first lead portion, with the HTAM affixing the first clip to the first chip and the first lead portion.
Data Source
AI summary
A lead frame package includes a first semiconductor chip, a second semiconductor chip, and a first lead frame. The first semiconductor chip is connected to a die attachment pad using a first clip. The second semiconductor chip is connected to the die attachment pad using a second clip. The die attachment pad is sandwiched between the first semiconductor chip and the second semiconductor chip. The first lead frame is connected to the die attachment pad.