Dual-Chip Package Layout for Redundant Sensor Reliability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing electronic component packages face challenges in achieving improved operational reliability while maintaining a small size, particularly in sensor units where redundancy in the operation system is desired.
Innovation Solution
The electronic component package incorporates two electronic component chips on a single substrate, with terminals and conductors arranged to couple each chip independently, ensuring redundancy and reducing the risk of short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two electronic component chips are provided on a single substrate to implement redundancy, then operational reliability is improved, but device complexity increases
Solution Approach 1:
The patent divides the electronic component package into two independent operational systems, each consisting of a separate electronic component chip with its own terminals and conductors. This segmentation allows each chip to function independently, providing redundancy while maintaining manageable complexity through modular organization.
Solution Approach 2:
The patent creates a duplicate operational system by providing a second electronic component chip that mirrors the first chip's functionality. Each chip has corresponding terminals and conductors arranged similarly, enabling one chip to serve as a backup for the other, thus improving reliability through redundancy.
2Reliability
If terminals and conductors are arranged to couple each chip independently, then the risk of short circuits is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent employs asymmetric arrangement where terminals on the substrate are positioned such that terminals for the first chip are spatially separated from terminals for the second chip. This asymmetric layout prevents potential short circuits between chips while maintaining organized conductor paths that facilitate manufacturing.
Solution Approach 2:
The patent extracts the terminal coupling function into separate, dedicated conductor paths for each chip. By taking out the terminal connections and assigning them to specific conductors that only connect to their corresponding chip, the design eliminates cross-interference and simplifies the manufacturing process by reducing the need for complex routing rules.
3Reliability
If two electronic component chips are provided on a single substrate, then redundancy is achieved, but the package size increases
Solution Approach 1:
The patent utilizes the substrate surface area efficiently by arranging the two electronic component chips and their associated terminals in a compact two-dimensional layout. By optimizing the spatial distribution of chips, terminals, and conductors across the substrate plane, the package achieves redundancy without excessive size increase.
Solution Approach 2:
The patent merges the two electronic component chips and their support structures onto a single substrate, sharing common structural resources such as the substrate itself and the molding compound. This consolidation approach achieves redundancy while minimizing the overall package size by eliminating duplicate support structures.
Data Source
AI summary
An electronic component package has an outer edge including a first side and a second side adjacent to each other. The electronic component package includes a first electronic component chip, a second electronic component chip provided at a distance from the first electronic component chip, one or more first terminals disposed along the first side, one or more second terminals disposed along the second side, and one or more first conductors. The one or more first conductors couple the one or more first terminals to the first electronic component chip, with the one or more first terminals being uncoupled to the second electronic component chip.