Dual-Chip Semiconductor Package Layout for Thermal Isolation
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Solution Overview
Problem
The existing semiconductor packages with two semiconductor chips mounted on both sides of a lead frame face issues of heat conduction, performance deterioration, and warping due to heat generation, leading to potential failures and characteristic variations.
Innovation Solution
A semiconductor package design with two semiconductor chips mounted on separate islands of different lead frames, spaced apart, connected via common inner leads, and embedded in a mold resin with optional heat dissipation mechanisms such as a heat sink or heat-conductive resin to manage heat transfer and warping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If two semiconductor chips are mounted on both sides of one lead frame, then mounting area is reduced, but heat conduction between chips causes performance deterioration
Solution Approach 1:
The patent divides the mounting structure into separate lead frames (first lead frame and second lead frame) with islands spaced apart, rather than using a single lead frame. This segmentation physically isolates the two semiconductor chips, preventing heat conduction between them while maintaining compact packaging.
Solution Approach 2:
The patent introduces an insulating layer between the first island and second island that act as intermediary elements. This insulating layer blocks thermal conduction path between the chips while allowing electrical connections through conductive patterns, thus resolving the heat conduction issue.
2Area of stationary object
If two semiconductor chips are mounted on both sides of one lead frame, then mounting area is reduced, but heat causes warping of chips
Solution Approach 1:
By separating the chips onto different lead frames with spaced islands, the thermal load on each chip is isolated. This prevents cumulative heat effects that would cause warping, while the segmented structure maintains overall package compactness.
Solution Approach 2:
The insulating layer and spaced island configuration act as preventive measures against heat accumulation. By designing the structure to inherently block thermal paths before heat can cause warping, the patent prevents the problem rather than correcting it.
3Temperature
If islands are spaced apart to suppress heat conduction, then heat dissipation is improved, but device complexity increases
Solution Approach 1:
The insulating layer serves multiple functions simultaneously: it provides thermal insulation to prevent heat conduction, provides mechanical support for the spaced island configuration, and serves as a base for conductive patterns that enable electrical connections. This multi-functionality reduces overall device complexity despite the spaced configuration.
Solution Approach 2:
The patent combines the insulating layer, spacing structure, and electrical connection paths into an integrated configuration. The conductive patterns are formed on the insulating layer itself, merging thermal management and electrical connection functions into a unified structure rather than separate components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively suppresses heat conduction and warping, maintaining performance stability and reducing failures by optimizing heat dissipation and chip separation.
Implementation Method 1
a heat-conductive resin that dissipates heat, generated in one of the first semiconductor chip and the second semiconductor chip, to the frame-like member
Implementation Method 2
one of the first island and the second island may be embedded in the mold resin
Data Source
Figure 1
Figure 2
Figure 3a~3b
AI summary
The present technology suppresses performance deterioration caused by heat in a semiconductor package provided with two semiconductor chips. A semiconductor package includes a first semiconductor chip, a first lead frame, a second semiconductor chip, and a second lead frame. The first semiconductor chip is mounted on a first island of the first lead frame. A second island of the second lead frame is disposed at a predetermined spacing from the first island, and the second semiconductor chip is mounted on the second island.