Dual-Chip PCB Layout for HSM Tamper Detection
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Solution Overview
Problem
Current Hardware Security Modules (HSMs) face challenges in providing adequate tamper resistance and detection, as attackers can attempt to bypass existing security measures by accessing the active surfaces of chips or disrupting tamper detection features, compromising the security and reliability of the device.
Innovation Solution
The implementation of a dual-chip configuration with the main processor and tamper processor mounted on opposite sides of the PCB, with a tamper detection link routed through the PCB between them, making it difficult for attackers to access the active surfaces without triggering a tamper detection, and the use of conductive paths and via holes to form a secure loop that is hard to disable.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If chips are mounted with active surfaces facing outward for easy access, then ease of operation is improved, but tamper resistance deteriorates
Solution Approach 1:
The patent inverts the conventional mounting orientation by placing the active surface of the chip against the PCB rather than facing outward. This dimensional repositioning hides the active surface within the device structure, making it inaccessible to external tampering while maintaining electrical connectivity through the PCB interface.
2Ease of operation
If tamper detection links are made accessible for monitoring, then ease of operation is improved, but security deteriorates
Solution Approach 1:
The tamper detection link is routed through the PCB and positioned within the overlapping area of the two chips. This internal routing through a different spatial dimension (through the board rather than on the surface) allows the monitoring function to operate while being physically protected from external access and manipulation.
3Device complexity
If a single-chip design is used to reduce complexity, then device complexity is reduced, but security deteriorates
Solution Approach 1:
The device is divided into two separate processing chips, each with distinct security functions. The first chip handles primary processing while the second chip contains the tamper detection logic and cryptographic operations. This segmentation allows each component to be optimized for its specific security role while collectively providing enhanced protection through their coordinated interaction and overlapping physical arrangement.
Data Source
Figure 1A~1B
Figure 2A~2B
Figure 2C
AI summary
A device, comprising: a circuit board; a first processing component comprising a first chip, the first processing component mounted on a first side of the circuit board with an active surface of the first chip facing towards the circuit board; a second processing component comprising a second chip, the second processing component mounted on a second side of the circuit board with an active surface of the second chip facing towards the circuit board, wherein the second side of the circuit board is opposite to the first side of the circuit board, wherein the second processing component is mounted at least partially overlapping with the first processing component; and a first tamper detection link provided through the circuit board and in the area of overlap between the first processing component and the second processing component.