Dual-Sided Chip Power Wiring to Cut BEOL Routing Losses
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Solution Overview
Problem
The existing power distribution methods in semiconductor chips face challenges with space constraints and inefficiencies due to densely packed devices, leading to increased power losses and wiring complexity, particularly as devices decrease in size and become more densely connected.
Innovation Solution
A dual power/ground distribution system is implemented, where power and ground connections are provided from both the front side and back side of the chip through a traditional BEOL network and a new grind side power distribution network, respectively, allowing for more efficient routing and reduced power losses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If power connections are made larger to reduce power losses, then power distribution efficiency is improved, but space available for other connections is reduced
Solution Approach 1:
The patent introduces a new dimension by implementing power distribution networks on both the front side and back side of the chip. This dual-sided approach allows power connections to be routed in three-dimensional space rather than being constrained to a single planar layer, effectively increasing the available area for power distribution without occupying additional lateral space in the BEOL metallization layers.
2Area of stationary object
If devices are made smaller and more densely packed, then chip area is reduced, but power distribution complexity increases
Solution Approach 1:
The patent segments the power distribution system into multiple independent networks located on different sides of the chip. Each power distribution network (front side and back side) can be independently designed and optimized, allowing for simplified routing and reduced complexity in each individual network while maintaining high device density.
3Length of stationary object
If power connections are routed through upper BEOL layers, then distance to devices is reduced, but more space is consumed in densely packed metallization layers
Solution Approach 1:
The patent utilizes the vertical dimension by routing power connections through both upper and lower BEOL layers on opposite sides of the chip. This approach allows power connections to reach devices more directly by exploiting the third dimension (depth), thereby reducing lateral space consumption in the metallization layers while maintaining short connection lengths.
Data Source
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AI summary
A semiconductor chip comprises one or more bottom external (power or ground) connections, a front side power network layer, a device layer, and a grind side power network layer. The device layer has a plurality of devices. One or more of the devices has one or more device power connections and one or more device ground connections and the device layer has a front side and a back grind side. The front side power network layer has power, ground, signal, and other connections that connect to respective device power and device ground connections from/through the top front side layer. In like manner, power, ground, signal, and other connections connect to respective device power and device ground connections from/through the bottom of grind side power network layer. Accordingly, one or more first device power connections is connected to one or more of the front side power network layer connections, one or more second device power connections is connected to one or more of grind side power network connections so the front side power network layer and the grind side power network layer provide the device layer with a dual power/ground feed/distribution from both the top/back and bottom/front of the device layer of the chip.