Dual-Chip QFN Package Layout for Heat Dissipation and Signal Routing
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Solution Overview
Problem
Current packaging solutions for electronic chips with different substrate materials, such as gallium nitride and silicon, are not compatible, leading to inefficiencies in heat dissipation and complex connection routing, resulting in increased system bulk and manufacturing costs due to the need for separate packages tailored to each chip's specific constraints.
Innovation Solution
A quad flat no-leads package with a central heat-dissipating mounting plate and peripheral signal-transmitting array, thermally and electrically coupling electronic chips with different substrate materials, including gallium nitride and silicon, using connecting wires and ball grid arrays to manage heat dissipation and complex connections within a single package.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If a flat no-leads package is used for heat dissipation, then heat dissipation efficiency is improved, but connection routing complexity increases
Solution Approach 1:
The package is divided into distinct functional zones: a central mounting plate for thermal management and peripheral regions for electrical connections. This segmentation allows the heat-dissipating GaN chip to be positioned centrally while Si chips with complex routing requirements are placed in peripheral areas, resolving the contradiction between heat dissipation efficiency and connection routing complexity.
Solution Approach 2:
Different regions of the package are assigned different functional properties: the central mounting plate provides thermal conduction pathways, while peripheral areas provide electrical connection points. This local differentiation enables simultaneous optimization of heat dissipation in the center and complex electrical routing at the periphery.
2Reliability
If separate packages are designed for each chip type, then chip-specific constraints are satisfied, but system bulk increases
Solution Approach 1:
Multiple chip types with different substrate materials (GaN and Si) are merged into a single package structure. The package simultaneously accommodates high-power GaN chips requiring heat dissipation and complex-routing Si chips, thereby satisfying chip-specific constraints while reducing system bulk through integration.
Solution Approach 2:
The package structure is designed with universal compatibility to house different chip types with varying constraints. The mounting plate and connection grid provide multi-functional support for both thermal management and complex electrical routing, eliminating the need for separate dedicated packages.
3Reliability
If separate packages are designed for each chip type, then chip-specific constraints are satisfied, but manufacturing costs increase
Solution Approach 1:
Multiple chip types are combined in a single package, allowing simultaneous satisfaction of different chip-specific constraints through unified design. This merging reduces manufacturing costs by eliminating the need to produce and assemble multiple separate package types.
Solution Approach 2:
The package employs universal mounting and connection structures that can accommodate different chip types, simplifying the manufacturing process. The same package design and assembly procedures can be used regardless of which combination of chips is installed, thereby reducing manufacturing complexity and cost.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution allows for the cohabitation and electrical coupling of chips with varying thermal and electrical constraints, optimizing signal transmission and reducing system size and manufacturing costs by using a single package that adapts to both high-heat and complex connection requirements.
Implementation Method 1
a mounting plate having a first part, for example central, able to dissipate heat
Implementation Method 2
electrically coupled to the second chip as well as to the second part at least by means of connecting wires
Implementation Method 3
the second chip being thermally coupled to the first part and electrically coupled to the second part by means of at least a first array of connection balls
Data Source
AI summary
A package includes a mounting plate having a first part able to dissipate heat and a second part able to transmit and/or receive electrical signals. A cladding houses a first electronic chip and second electronic chip. The first electronic chip has a first semiconductor substrate (giving off, in operation, a first quantity of heat) mounted to the first part of the mounting plate and electrically connected by wires to the second part of the mounting plate. The second electronic chip has a second semiconductor substrate (giving off, in operation, a second quantity of heat) mounted to an interposer support including an interconnection network. An array of connection balls interconnects the interposer support to the first part of the mounting plate and the second part of the mounting plate. The first and second semiconductor substrates are different.