Dual Chip Select EMIF for Page Mode Flash Access
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Solution Overview
Problem
Processor devices without native support for page mode access timings experience performance loss when accessing page mode flash memory, as they are forced to use slower access timings for all accesses within a page, leading to longer load times for large blocks of code/data.
Innovation Solution
The implementation of a dual chip select approach within the external memory interface (EMIF) allows for configuration of slower access timings for the first word of a page and faster timings for subsequent words, enabling efficient page mode access without additional logic, using existing EMIF control logic and leveraging DMA capabilities for chained transfers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a processor device uses a generic asynchronous external memory interface without native page mode support, then the device complexity is reduced and compatibility is improved, but the access speed to flash memory deteriorates due to slower access timings being used for all accesses
Solution Approach 1:
The patent segments the flash memory access into two distinct phases: a first access phase using slower timings configured for the first word of a page, and a second access phase using faster timings configured for subsequent words in the page. This segmentation allows the generic EMIF to achieve page mode performance by treating different accesses within the same page differently, thereby resolving the contradiction between maintaining simple generic interface design and achieving fast page mode access speeds.
2Productivity
If a processor device implements native page mode support in the EMIF, then the access speed to flash memory is improved, but the device complexity increases and compatibility with existing devices decreases
Solution Approach 1:
The patent makes the generic EMIF multi-functional by enabling it to support both traditional single-access modes and page mode accesses through configuration of timing parameters. By using existing EMIF control logic to manage two different timing configurations, the system achieves page mode performance without requiring dedicated page mode hardware, thus maintaining universality while improving productivity.
3Loss of time
If a processor device uses slower access timings for all flash memory accesses, then the device complexity is reduced and ease of operation is improved, but the access time increases significantly
Solution Approach 1:
The patent introduces dynamic timing adjustment where the EMIF automatically switches between two timing configurations based on the access phase. The first timing configuration is used for the initial access to a page, and the second timing configuration is used for subsequent accesses within the same page. This dynamic adaptation reduces access time significantly while maintaining operational simplicity through automatic timing management.
Data Source
AI summary
A method is provided for accessing a memory device having pages by a memory interface that does not directly support page accesses. A first memory space of the memory interface is configured with a first set of timing parameters and a second memory space of the memory interface is configured with a second set of timing parameters. A page mode access is initiated to a page of the memory device using the first memory space of the memory interface for at least a first data transfer and continued using the second memory space of the memory interface for a plurality of data transfers.