Dual-Class Redundancy for Integrated Circuit Error Handling
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Solution Overview
Problem
Existing programmable integrated circuits face challenges in providing real-time error detection and correction while minimizing resource usage and operational delays due to errors caused by transistor aging or soft errors, as current redundancy methods like triple modular redundancy are costly and inefficient.
Innovation Solution
Implementing a dual-class circuitry approach where control circuitry uses triple modular redundancy for real-time error correction and datapath circuits use double modular redundancy with real-time error detection and background error checking, allowing for error correction with reduced resource usage and minimal operational disruption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If triple modular redundancy is used for error correction, then error resiliency is improved, but resource usage increases significantly
Solution Approach 1:
The patent segments circuitry into two distinct classes: control circuitry (error-sensitive) and datapath circuitry (error-tolerant). This segmentation allows different redundancy strategies to be applied to each class, optimizing resource usage while maintaining error resiliency where most needed.
Solution Approach 2:
The patent applies local quality by implementing triple modular redundancy specifically for control circuitry while using double modular redundancy for datapath circuitry. This localized application of redundancy ensures error correction capabilities are concentrated where they provide maximum benefit while reducing overall resource consumption.
2Reliability
If background error checking is performed, then error detection capability is improved, but operational delay increases
Solution Approach 1:
The patent implements periodic background error checking that operates independently of the main data processing flow. This periodic action allows error detection to occur without continuously interrupting normal operations, thereby maintaining error detection capability while minimizing operational delays.
Solution Approach 2:
The patent performs preliminary error checking on configuration data before it is fully loaded into circuitry. This preliminary action identifies and corrects errors proactively, preventing them from causing operational delays during critical processing phases.
3Reliability
If real-time error detection is implemented, then error resiliency is improved, but circuit resource requirements increase
Solution Approach 1:
The patent implements dynamic error detection where the intensity and type of redundancy applied varies based on the error sensitivity of different circuit components. Control circuitry receives full triple modular redundancy with real-time detection, while datapath circuitry receives lighter double modular redundancy, creating a dynamic resource allocation strategy.
Solution Approach 2:
The patent changes the redundancy parameter across different circuit classes, applying triple modular redundancy to control circuitry and double modular redundancy to datapath circuitry. This parameter change optimizes the balance between error resiliency and resource requirements by matching redundancy levels to actual error sensitivity.
Data Source
AI summary
A logic design may include control and datapath circuitry. The datapath circuitry may be implemented in a double modular redundancy arrangement that generates respective first and second data signals. The control circuitry may be implemented in a triple modular redundancy arrangement. Storage circuitry may be used to buffer the first and second data signals. Real-time error detection circuitry may perform real-time error detection operations on the first and second data signals. Background error checking circuitry may perform background error checking operations such as cyclic redundancy check calculations on configuration data. In response to an error detected by the real-time error detection circuitry, the circuitry may select between the buffered first and second data signals to produce the output data signal. The selection may be performed based on the background error checking operations and may be delayed relative to the real-time detection of the error.