Dual-Clock ADC Sampling for Constant-Rate Digital Output
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Solution Overview
Problem
Current analog-to-digital converters require complex processing to adjust sampling rates when performing undersampling due to changes in analog input signal frequency and bandwidth, complicating the conversion process and necessitating additional sampling rate conversion in digital circuits.
Innovation Solution
The proposed analog-to-digital converter employs a sample-and-hold circuit synchronized with a first sampling clock, a filter circuit to smooth the output, and an analog-to-digital converter circuit synchronized with a second sampling clock, allowing for flexible sampling timing and maintaining a constant sampling rate for digital output, even when the first sampling clock frequency changes, thus eliminating the need for complex sampling rate conversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single sampling clock is used for both sample-and-hold and ADC circuits, then synchronization is simplified, but the sampling rate must be changed when analog input signal frequency and bandwidth change, complicating the conversion process
Solution Approach 1:
The patent divides the sampling function into two independent sampling circuits: a first sampling circuit that samples the analog input signal at a first sampling rate, and a second sampling circuit that samples the held signal at a second sampling rate. This segmentation allows each circuit to operate independently with different sampling rates, eliminating the need for complex sampling rate conversion while maintaining adaptability to different signal frequencies and bandwidths.
Solution Approach 2:
The patent introduces a sample-and-hold circuit as an intermediary between the first sampling circuit and the second sampling circuit. The sample-and-hold circuit holds the sampled analog signal during the interval between the first sampling moment and the second sampling moment, enabling the two sampling circuits to operate with different sampling rates without direct synchronization requirements.
2Productivity
If sampling rate is changed to match analog input signal frequency, then undersampling is achieved, but additional sampling rate conversion in digital circuits is required
Solution Approach 1:
The patent segments the sampling process into two distinct stages with different sampling rates. The first sampling circuit performs initial sampling at a rate optimized for the analog input signal frequency, achieving undersampling when appropriate. The second sampling circuit then samples the held signal at a different rate suitable for digital processing. This segmentation eliminates the need for additional sampling rate conversion in digital circuits because both sampling operations are already performed at optimal rates for their respective stages.
3Adaptability or versatility
If first sampling clock frequency is changed to adapt to different bands, then versatility is improved, but constant sampling rate for digital output is compromised
Solution Approach 1:
The patent segments the sampling function into two independent parts: the first sampling circuit uses a first sampling clock whose frequency can be changed to adapt to different analog input signal bands and frequencies, while the second sampling circuit uses a second sampling clock that maintains a constant frequency for stable digital output. This segmentation allows the first sampling clock to be flexible for band compatibility while the second sampling clock ensures output signal stability.
Solution Approach 2:
The sample-and-hold circuit acts as an intermediary that decouples the frequency variations of the first sampling clock from the second sampling clock. When the first sampling clock frequency changes to adapt to different bands, the sample-and-hold circuit holds the sampled signal, allowing the second sampling clock to operate at a constant frequency and produce a stable digital output signal.
Data Source
AI summary
An analog-to-digital converter (1) includes an S/H circuit (10) that samples and holds an analog input signal in synchronization with a first sampling clock signal (CLK1), a filter circuit (20) that smooths an output signal of the S/H circuit (10), and an ADC circuit (30) that samples an output signal of the filter circuit (20) in synchronization with a second sampling clock signal (CLK2) different from the first sampling clock signal (CLK1), and outputs a digital signal corresponding to an amplitude of the output signal that is sampled.