Dual-Clock Data Recording for Duty Cycle Distortion Tolerance
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Solution Overview
Problem
Current processor and memory emulation technologies face challenges in accurately modeling cache events and system interactions, leading to performance discrepancies between simulated and actual target performance, especially with cache-based architectures, which affects developer confidence and debugging efficiency.
Innovation Solution
The implementation of advanced emulation features, including data recording using two out-of-phase clocks to mitigate duty cycle distortion, adaptive calibration for skew adjustments, and enhanced trace data compression and recording techniques, provides better visibility into system and memory behavior, enabling more accurate profiling and debugging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single clock is used for data extraction, then the logic is simpler, but the system is highly sensitive to duty cycle distortion from components
Solution Approach 1:
The patent combines two clock signals (in-phase and out-of-phase) into a single data extraction system. By merging multiple clock sources, the system achieves tolerance to duty cycle distortion while maintaining relatively simple extraction logic. The combined clocking approach allows the data extraction to function reliably even when individual clock duty cycles are distorted.
Solution Approach 2:
The patent uses a composite clocking approach where two different clock signals (with different phase relationships) are combined to create a robust data extraction system. This composite clocking strategy is analogous to using composite materials - combining two signals with different characteristics to achieve properties (tolerance to distortion) that neither signal alone could provide.
2Reliability
If two out of phase clocks are used for data extraction, then tolerance to duty cycle distortion improves, but the logic complexity increases
Solution Approach 1:
The patent segments the clocking function into two separate clock signals (in-phase and out-of-phase) that operate independently. This segmentation allows each clock to be optimized for its specific phase relationship with the data, improving overall tolerance to duty cycle distortion. The segmented approach breaks down the complex timing requirement into manageable, independent clocking functions.
3Loss of information
If advanced emulation features are implemented, then visibility into system behavior improves, but the device complexity increases
Solution Approach 1:
The patent introduces trace recording functionality as an intermediary mechanism between the actual system operation and the developer's observation. This intermediary captures system behavior (including duty cycle distortion effects) and presents it in a visible format, allowing developers to observe system behavior without adding significant complexity to the core operational logic.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
These features enhance debug and profiling capabilities, reducing the gap between simulated and actual performance, improving developer confidence, and enabling more effective optimization and debugging of cache-related issues.
Implementation Method 1
Data recording of single ended signals may use two out of phase clocks to extract the data
Data Source
AI summary
Data from both a positive edge sample and negative edge sample are used to determine a data bit. The primary and secondary clocks capture two copies of the data. A sample is taken with a positive edge of one clock and the negative edge of the other clock each bit period. These two captured data values are combined along with the data value captured by the previous negative edge to determine the data bit value. The captured data may be dynamically de-skewed previous to being clocked into a buffer based on the clock edges sampling the data.