Dual-Source Clock Generator for Interruption-Free Failover
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Solution Overview
Problem
Current clock generation circuits experience interruptions in clock signal output when a primary clock source fails, leading to unreliable operation.
Innovation Solution
A clock generation circuit comprising a first and second clock source, each with an oscillation circuit and a direct current bias circuit, where the direct current bias circuit removes direct current components and superimposes a specific voltage on the clock signals, and a logic gate performs an AND or OR logical operation on these signals to generate a continuous clock signal, ensuring uninterrupted output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dedicated detection circuit is arranged to detect primary clock source failure and switch to secondary clock source, then reliability of the clock generation circuit is improved, but a time period is taken from when the primary clock source stops outputting to when the detection circuit detects the failure and switches to the secondary clock source, during which the clock generation circuit cannot provide a correct clock signal
Solution Approach 1:
The patent applies preliminary action by performing logical operations on clock signals before actual failure occurs. The logic gate circuit continuously processes signals from both primary and secondary clock sources, preparing the system to immediately output a valid clock signal from the secondary source when the primary source fails, eliminating detection and switching time delays.
Solution Approach 2:
The patent ensures continuity of useful action by using a logic gate circuit that continuously outputs a clock signal by combining inputs from both primary and secondary clock sources. When one source fails, the other continues to provide the output without interruption, maintaining continuous useful action throughout the system.
2Reliability
If two clock sources are arranged in the clock generation circuit with a detection circuit, then the clock generation circuit can switch to a secondary clock source when the primary fails, but the detection and switching process causes clock signal interruption
Solution Approach 1:
The patent merges the outputs of two clock sources through a logic gate circuit. The logic gate combines the primary clock signal and secondary clock signal inputs, allowing the system to utilize both sources simultaneously in a unified output structure, ensuring that when one source fails, the other immediately takes over without interruption.
Solution Approach 2:
The logic gate circuit maintains continuous useful action by continuously processing inputs from both clock sources and providing an uninterrupted output. The system ensures that the clock signal generation continues without interruption by having the logic gate always ready to output a valid signal from either source.
Data Source
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AI summary
A clock generation circuit and a clock signal generation method are disclosed. In the method, a direct current bias circuit in a first clock source superimposes a first direct current voltage on a first clock signal output by a first oscillation circuit, to generate a second clock signal; and a logical operation is performed on the second clock signal and a third clock signal that is generated by a second clock source, to generate a fourth clock signal. The fourth clock signal is used as a signal output by a clock generation circuit. In the method, when the first oscillation circuit cannot normally work, the clock generation circuit can still output a correct clock signal. This avoids clock signal interruption when switching is performed from the first clock source to the second clock source.