Dual-Clock Circuit Failure Detection for Sensor Operation Continuity
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Solution Overview
Problem
Existing circuit devices that rely on clock signals from physical quantity transducers are prone to failure, leading to complete system shutdowns and inability to detect errors, as external devices cannot accurately determine the presence or absence of errors without functioning interface circuits.
Innovation Solution
A circuit device incorporating a master clock signal generation circuit, a master clock signal failure detection circuit, and a control circuit that operates independently of the transducer's clock frequency, allowing for partial operation and error detection even when the transducer's clock signal fails, using a separate error detection clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the circuit device operates entirely on the clock signal from the physical quantity transducer, then the system can be simplified, but the reliability deteriorates because the entire system stops when the clock signal fails
Solution Approach 1:
The circuit device is divided into multiple operational segments: a first operating section that uses the transducer clock signal for vibration driving, and a second operating section that uses a separate master clock signal for control functions. This segmentation allows different parts of the system to use different clock sources, maintaining operation continuity when one clock fails.
Solution Approach 2:
A master clock signal generation circuit is introduced as an intermediary clock source that is independent of the transducer clock signal. This intermediary provides an alternative timing reference when the transducer clock fails, allowing the control circuit to continue operating and detect the failure condition.
2Device complexity
If the defect diagnosis circuit uses the same clock signal as the interface circuit, then the circuit can be simpler, but the ability to detect and report errors deteriorates when the clock signal fails
Solution Approach 1:
The master clock signal acts as an intermediary timing source that enables the defect diagnosis circuit to independently of the transducer clock. This allows error detection and information output to continue even when the transducer clock fails, preventing loss of diagnostic information.
3Adaptability or versatility
If the control circuit operates at the driving frequency of the vibrator, then the system can be more integrated, but the processing speed deteriorates and becomes insufficient for control operations
Solution Approach 1:
The system separates vibration driving functions from control functions by assigning them different clock sources. The vibration driving operates at the transducer's resonant frequency, while the control circuit operates at the higher-frequency master clock signal, enabling both functions to operate optimally without speed limitations.
Solution Approach 2:
The clock frequency parameter is changed for different operational sections. The control circuit uses the master clock signal with a frequency suitable for high-speed processing, while the vibration driving uses the transducer clock signal at the resonant frequency, optimizing both performance and integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables continued operation of critical circuit components and reliable error detection and reporting, preventing system-wide failures and improving diagnostic capabilities.
Implementation Method 1
a driving circuit that generates a clock signal by oscillating a vibrator
Data Source
AI summary
A circuit device includes a driving circuit that generates a clock signal by oscillating a vibrator, a master clock signal generation circuit that generates a master clock signal, and a master clock signal failure detection circuit that detects a failure of the master clock signal. The master clock signal failure detection circuit detects the failure of the master clock signal on the basis of an error detection clock signal, which is the clock signal from the driving circuit, and the master clock signal.