Dual Clock Generator Frequency Control
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Solution Overview
Problem
Selecting an optimum processor clock frequency is challenging due to interdependencies between voltage, current, temperature, and execution frequency, particularly in processors handling demanding workloads while adhering to power budgets, as increasing frequency enhances execution efficiency but increases power consumption.
Innovation Solution
A method involving two clock generators, where the frequency of the first clock generator is reduced when a power budget is exceeded, switching to a second clock generator with a lower frequency, and then reverting to the first generator after a predetermined time, allowing for dynamic adjustment of processor clock frequency to balance efficiency and power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the processor clock frequency is increased to improve execution efficiency, then the processing speed and efficiency are improved, but the power consumption increases and may exceed the power budget
Solution Approach 1:
The patent implements dynamic clock frequency adjustment by switching between multiple clock generators based on power budget conditions. The system dynamically selects between a first clock generator (higher frequency) and a second clock generator (lower frequency) to adapt processing speed to available power, resolving the contradiction between execution efficiency and power consumption.
Solution Approach 2:
The system changes the clock frequency parameter by selecting different clock generators with different frequency characteristics. This allows the processor to operate at optimal frequencies within power budget constraints, improving execution efficiency without exceeding power limits.
2Device complexity
If a single clock generator is used to simplify the system, then the device complexity is reduced, but the ability to adapt to varying power budgets and workloads is limited
Solution Approach 1:
The patent makes the clock generation system multi-functional by incorporating multiple clock generators that can serve different purposes. The first clock generator handles normal operations, while the second clock generator provides power-constrained operation. This universal design allows the system to adapt to various power budgets and workload types without requiring completely different hardware configurations.
Data Source
AI summary
There is disclosed a method of controlling the frequency of a clock signal in a processor. The method selects a first clock generator to provide a processor clock signal for executing an application. If a threshold event is detected, a second clock generator is selected. The method reduces the frequency of a clock signal generated by the first clock generator while a processor clock signal is being provided for execution of an application from the second clock generator. The second clock generator generates a clock at a lower speed than the first clock generator. After a predetermined time, the first clock generator is reselected to provide the processor clock signal. The threshold detection is repeated until an optimum clock frequency is discovered.