Dual Clock Rate Image Processing for Preview and Capture Modes

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Solution Overview

Problem

Conventional image processing systems in portable devices experience delays and conflicts during image capture due to low clock frequencies, leading to distorted images of moving objects and inefficient data processing, particularly when handling high-resolution images.

Innovation Solution

An image processing method and device that utilize a dual clock rate system, where the first processing clock rate is lower for generating YUV data and increases to a second processing clock rate for encoding, allowing for prompt encoding and transmission of valid data, while preventing conflicts by skipping the input of raw data for the next frame during encoding.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If a low clock frequency is used for image processing, then power consumption is reduced, but image capture delay increases and processing speed decreases

Engineering Contradiction:
Improvepower consumptionVSAvoidimage capture delay
Core Design Contradiction:
Use of energy by moving objectVSLoss of time

Solution Approach 1:

The system dynamically adjusts the clock frequency based on the operating mode: using a first (lower) clock frequency during preview mode to save power, and switching to a second (higher) clock frequency during capture mode to reduce processing delay and improve encoding speed

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The invention changes the clock frequency parameter according to different processing stages and modes, optimizing the balance between power consumption and processing performance by selecting appropriate frequency values for preview versus capture operations

Inventive Principle:
Principle #35Parameter changes

2Use of energy by moving object

If a low clock frequency is used for image processing, then power consumption is reduced, but processing speed decreases

Engineering Contradiction:
Improvepower consumptionVSAvoidprocessing speed
Core Design Contradiction:
Use of energy by moving objectVSProductivity

Solution Approach 1:

The system dynamically adjusts the clock frequency based on the operating mode: using a first (lower) clock frequency during preview mode to save power, and switching to a second (higher) clock frequency during capture mode to reduce processing delay and improve encoding speed

Inventive Principle:
Principle #15Dynamics

3Use of energy by stationary object

If data for the next frame is input during encoding of the current frame, then data transmission continuity is improved, but data conflicts occur causing encoding errors

Engineering Contradiction:
Improvedata transmission continuityVSAvoidencoding accuracy
Core Design Contradiction:
Use of energy by stationary objectVSReliability

Solution Approach 1:

The system prepares and buffers data for the next frame in advance during preview mode, so that when capture mode begins, the data is already ready and can be transmitted without conflict during the high-priority encoding process

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The invention introduces a buffer or intermediate storage mechanism that decouples the data transmission stream from the encoding process, allowing data for the next frame to be staged without interfering with the encoding of the current frame

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS8018499B2Image processing method and device using different clock rates for preview and capture modes
Publication Date: 2011.09.13 MILA US INC
  • US8018499B2 patent drawing
  • US8018499B2 patent drawing
  • US8018499B2 patent drawing

AI summary

An image processing method and a device thereof are disclosed. In an image signal processor of the present invention, a process clock rate or an output clock rate for a preview mode is applied differently from a process clock rate or an output clock rate for a capture mode. When performing the capture mode, however, the process clock rate can be controlled to be the same as or larger than the output clock rate. With the present invention, the lagging can be reduced during the image processing.