Dual-Clock Latch Circuit for Single Event Transient Tolerance
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Solution Overview
Problem
High-energy radiation can cause Single Event Transients (SETs) in semiconductor integrated circuits, leading to errors and malfunctions, particularly in latch circuits due to disturbances in clock signals, which existing technologies have not adequately addressed in terms of tolerance enhancement.
Innovation Solution
A latch circuit design utilizing two independent clock signal lines, where data is transmitted or held based on the states of these signals, ensuring that transient variations in one clock signal do not affect the data retention unit, thereby preventing malfunction and data rewrite.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single clock signal line is used to control the latch circuit, then the circuit operation is simple, but the circuit becomes vulnerable to SET-induced clock disturbances causing malfunction and data rewrite
Solution Approach 1:
The clock signal control function is segmented into two independent clock signal lines (first clock signal and second clock signal) that both control the same data input unit and data retention unit. This segmentation allows the circuit to tolerate SET disturbances because a transient error in one clock line does not affect the other, thereby resolving the contradiction between reliability and complexity by distributing the control function across multiple independent signal paths.
2Reliability
If data is held at a single node, then the circuit structure is simple, but transient clock variations can cause unintended data changes
Solution Approach 1:
The data storage function is merged into a shared node that is controlled by multiple independent clock signals. Instead of having separate storage nodes for each clock signal, the invention combines the data holding function into a single node that responds to either clock signal's valid state. This merging approach maintains data stability during SET events while avoiding the complexity of multiple independent storage structures.
Data Source
AI summary
A latch circuit has: a data input unit to which an input data is input; and a data retention unit including a node connected to the data input unit. The data input unit transmits a data depending on the input data to the node, when both of a first clock signal and a second clock signal that are driven independently from each other are at a first level. The data retention unit holds a data at the node, when at least one of the first clock signal and the second clock signal is at a second level that is an inverted level of the first level.