Latency Detection Using Dual Clocks to Prevent SLA Violations

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Solution Overview

Problem

Conventional systems for determining latency in computer systems, such as switches, are inadequate as they rely on simple counting mechanisms that lead to inaccurate latency estimation due to wrapping around of clocks, potentially allowing excessive latency to go undetected, which can violate service level agreements (SLAs).

Innovation Solution

Implementing a system that uses two or more clocks, where one clock counts at a constant rate and the other is modified by a random element after reaching its maximum value, allowing for accurate determination of latency by calculating the time between task enqueuing and dequeuing across both clocks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single clock counts time in cycles from zero to maximum before resetting, then the system is simple to implement, but the latency measurement becomes inaccurate when the clock wraps around

Engineering Contradiction:
Improveclock system complexityVSAvoidlatency measurement accuracy
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The patent divides the timing measurement function into multiple independent clocks, each responsible for measuring specific time intervals. This segmentation allows the system to overcome the wrapping limitation of a single clock by using multiple clocks to cover different time ranges, thereby improving measurement accuracy without requiring a single complex clock system.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a new dimension to time measurement by using multiple clocks operating simultaneously. Instead of relying on a single clock's linear counting, the system uses multiple clocks to create a multi-dimensional time measurement space, allowing accurate measurement of latency even when individual clocks wrap around.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If a clock reaches maximum value and wraps around to zero, then the counting mechanism continues without interruption, but the estimated latency becomes significantly underestimated

Engineering Contradiction:
Improvecontinuous counting capabilityVSAvoidlatency estimation accuracy
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The patent implements feedback mechanisms where the system monitors clock values and detects when a clock has wrapped around. Based on this feedback, the system adjusts the latency calculation to account for the wrapping, ensuring accurate measurement while maintaining continuous operation. The feedback loop allows the system to correct measurement errors caused by clock wrapping.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent replaces the mechanical single-clock counting system with a multi-clock system that uses different counting mechanisms. By substituting the single-clock approach with multiple clocks, the system eliminates the wrapping problem while maintaining continuous counting capability, as each clock can be independently managed and synchronized.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Device complexity

If conventional single-clock systems are used, then the system remains simple and efficient, but excessive latency may go undetected due to wrapping blind spots

Engineering Contradiction:
Improvetiming system complexityVSAvoidlatency detection reliability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent segments the timing detection function across multiple clocks, each monitoring specific time intervals. This segmentation eliminates blind spots where latency could go undetected, as multiple clocks provide overlapping coverage that ensures all latency values, including those exceeding the maximum clock count, are reliably detected.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent adds another dimension to latency detection by using multiple clocks simultaneously. This multi-dimensional approach creates a comprehensive monitoring framework that detects excessive latency reliably, as the system can identify when a task exceeds the maximum clock count by observing the relationships between multiple clock values.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

4Measurement precision

If multiple clocks are used to measure latency accurately, then latency detection precision improves, but the system complexity increases

Engineering Contradiction:
Improvelatency measurement accuracyVSAvoidclock system complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent designs multiple clocks to serve universal purposes in latency measurement. Each clock is engineered to perform the same basic function of timing measurement, but collectively they provide enhanced accuracy. The clocks are synchronized and coordinated to work together as a unified system, achieving multi-functionality that improves measurement precision without proportionally increasing complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12120035B2Latency detection using multiple clocks, including determination of whether latency exceeds a threshold
Publication Date: 2024.10.15 MELLANOX TECHNOLOGIES LTD(IL)
  • US12120035B2 patent drawing
  • US12120035B2 patent drawing
  • US12120035B2 patent drawing

AI summary

A device, a switch, and a method of determining latency which exceeds a threshold are described. A task is enqueued and a time is determined based on two clocks. A time the task is dequeued is determined based on the two clocks. Based on the time of enqueue and the time of dequeue according to each of the two clocks, the task is identified as meeting or violating a service level agreement.