Dual Clock Low-Power Mode Management
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current electronic systems face challenges in accurately managing low-power modes, particularly in maintaining system time accuracy when frequently transitioning between low-power and active modes.
Innovation Solution
The implementation of a method using two clocks, a first clock for a real-time counter and a second, faster clock for a system time counter, where values are saved and restored on specific clock edges, ensuring accurate system time recovery upon exiting low-power mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If a single slow clock is used for timing in low-power mode, then power consumption is reduced, but system time accuracy deteriorates when frequently transitioning between modes
Solution Approach 1:
The patent divides the timing function into two separate clocks: a first slow clock that operates in low-power mode to minimize energy consumption, and a second fast clock that operates in active mode to provide high-precision timekeeping. This segmentation allows each clock to be optimized for its specific operational context, resolving the contradiction between power savings and time accuracy.
Solution Approach 2:
The patent introduces a controller as an intermediary that manages the synchronization between the slow first clock and the fast second clock. The controller calculates time offsets and adjusts the fast clock's timing based on the slow clock's progression, enabling accurate system time maintenance while the system operates in low-power mode. This intermediary mechanism allows the system to reconcile the different timing rates without requiring both clocks to operate simultaneously at full power.
2Use of energy by stationary object
If the fast clock is deactivated in low-power mode, then power consumption decreases, but time recovery accuracy upon mode exit deteriorates
Solution Approach 1:
The patent applies preliminary action by having the controller continuously track the relationship between the slow first clock and the fast second clock even when the fast clock is deactivated. The controller pre-calculates time offsets and maintains synchronization data, so that when the system exits low-power mode, the time recovery process can immediately use these pre-computed values to restore accurate system time without requiring the fast clock to have been running throughout the low-power period.
Data Source
AI summary
In an embodiment a method for managing a low-power mode of an electronic device includes at a first request for transitioning an electronic device to a low-power mode, storing values of a first counter and a second counter of the electronic device on a first edge of a first clock and at a second request for transitioning the electronic device out of the low-power mode calculating a number of periods of a second clock between a second edge of the first clock and the first edge, the second edge being later than the first edge and updating the value of the second counter with a calculated value, wherein the first clock drives the first counter and the second clock drives the second counter, the second clock being faster than the first clock.