Dual Clock Signal Architecture for Memory Power Reduction
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Solution Overview
Problem
Modern memory devices often consume excessive power and incur unnecessary design constraints due to the use of double-frequency clock signals for processing command and address data, even when these data are not received as frequently as memory access operations, particularly in battery-operated devices.
Innovation Solution
A method and apparatus that utilize a first clock signal with a lower frequency for command processing and a second clock signal with a higher frequency for data access operations, reducing power consumption and simplifying timing requirements for data transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a double-frequency clock signal is used to process command data and address data in the memory device, then the data transfer rate is improved, but the power consumption increases
Solution Approach 1:
The patent segments the clock signal usage by introducing two separate clock signals: a first clock signal for command data and address data processing, and a second double-frequency clock signal for data access operations. This segmentation allows the memory device to use the higher frequency clock only when needed for data transfers, while using the lower frequency clock for command processing, thereby reducing overall power consumption while maintaining high data transfer rates.
Solution Approach 2:
The patent changes the frequency parameter of the clock signal based on the operation type. For command data and address data, a lower frequency first clock signal is used. For data access operations requiring high speed, a higher frequency second clock signal is used. This dynamic parameter change optimizes the balance between power consumption and data transfer rate.
2Productivity
If a double-frequency clock signal is used to process command data and address data, then the data transfer rate is improved, but the timing requirements and design constraints increase
Solution Approach 1:
The patent segments the timing requirements by associating different clock signals with different operation types. The first clock signal governs timing for command data and address data, while the second clock signal governs timing for data access operations. This segmentation simplifies the timing design by allowing each clock signal to have its own independent timing requirements, rather than all operations needing to conform to the stricter double-frequency timing.
Solution Approach 2:
The patent changes the frequency parameter of the clock signal based on the operation type. For command data and address data, a lower frequency first clock signal is used. For data access operations requiring high speed, a higher frequency second clock signal is used. This dynamic parameter change optimizes the balance between power consumption and data transfer rate.
Data Source
AI summary
Embodiments of the invention generally provide a method and apparatus for transmitting and receiving clock signals. In one embodiment, the method includes receiving, at a memory device, a first clock signal and a second clock signal. The frequency of the first clock signal may be less than the frequency of the second clock signal. The method further includes performing two or more data access operations using the second clock signal. One of the two or more data access operations may include a read operation and one of the two or more data access operations may include a write operation. The method also includes performing a command processing operation using the first clock signal.