Dual-Clock Noise Removal Circuit for Short Pulse Suppression
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Solution Overview
Problem
Existing semiconductor devices with noise removal circuits face challenges in effectively removing noise from control signals due to limitations in internal clock signal frequency and the number of latch stages, which affects the precision and ability to follow changes in control signals.
Innovation Solution
A semiconductor device with an improved noise removal circuit comprising first and second holding circuits, a majority determining circuit, and an output holding circuit, where flip flops or latch elements hold and process control signals in synchronization with internal clock signal timings, allowing for efficient noise removal without additional external components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of latch stages in the noise removal circuit is increased, then the precision of noise removal is improved, but the internal clock signal frequency must be higher to maintain the same processing speed
Solution Approach 1:
The patent divides the noise removal process into two independent paths: a first path using a first internal clock signal for initial noise removal, and a second path using a second internal clock signal (different frequency) for further noise removal. This segmentation allows each path to operate with optimized latch stage counts suitable for their respective clock frequencies, achieving high precision without requiring excessively high clock speeds in a single path.
Solution Approach 2:
The patent employs multiple internal clock signals with different frequencies dynamically. The first internal clock signal operates at one frequency while the second internal clock signal operates at another frequency, allowing the system to adapt the timing characteristics to the specific noise removal requirements at each stage, thereby resolving the contradiction between precision and speed requirements.
2Device complexity
If the internal clock signal frequency is lowered, then power consumption and circuit complexity are reduced, but the ability to follow changes in control signals deteriorates
Solution Approach 1:
The patent uses multiple internal clock signals with different frequencies to dynamically match the timing requirements of different circuit stages. This allows the circuit to maintain high-speed response capability where needed while using lower frequencies in other stages, thereby reducing overall power consumption and complexity without sacrificing the ability to follow signal changes.
Solution Approach 2:
The patent changes the frequency parameter of the internal clock signals used in different paths of the noise removal circuit. By using a first internal clock signal at one frequency and a second internal clock signal at another frequency, the system optimizes the balance between response speed and power consumption/complexity for each specific function.
3Device complexity
If the number of latch stages is reduced, then circuit complexity is reduced, but the precision of noise removal is reduced
Solution Approach 1:
The patent segments the noise removal function into multiple paths with different numbers of latch stages. The first path has a first number of latch stages operating with a first internal clock signal, while the second path has a second number of latch stages operating with a second internal clock signal. This segmentation allows each path to be optimized independently, achieving high overall precision without requiring all paths to have high complexity.
Solution Approach 2:
The patent varies the number of latch stages parameter in different paths of the circuit. By using different numbers of latch stages in conjunction with different internal clock signal frequencies, the system achieves high noise removal precision while keeping individual path complexities manageable.
Data Source
AI summary
A noise removal circuit is provided having a first holding circuit (20) and a second holding circuit (22) which holds a value of an input signal (IN) at a plurality of different timings in synchronization with rising and falling of an internal clock signal (ICL) generated within a semiconductor device, and which removes noise of the input signal (IN) according to the held value.