Dual Clock Phase Compensation for Low-Voltage Skew Control
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Solution Overview
Problem
The varying degrees of delay in clock signal propagation through buffers in clock trees of system-on-chips (SoCs) cause phase differences and clock skew, especially at lower operating voltages, leading to errors in data propagation and limiting the reduction of operating voltages due to non-linear variations that current engineering design aid (EDA) tools fail to predict effectively.
Innovation Solution
A dual clock tree system is implemented with programmable phase shifting, where a first and second input clock are generated with the second clock having a programmable phase shift relative to the first, used to create a composite clock signal that compensates for delay variations, allowing robust clocking at low voltages without additional buffering, which minimizes layout and power requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If operating voltage is decreased to save power, then energy consumption is reduced, but clock skew and phase differences increase due to non-linear delay variations in buffers
Solution Approach 1:
The patent applies preliminary action by pre-adjusting the phase of the clock signal before it propagates through the buffer tree. A phase adjustment circuit modifies the clock phase in advance to compensate for the expected non-linear delay variations that will occur at lower operating voltages, thereby preventing clock skew and phase differences before they affect signal integrity
Solution Approach 2:
The patent changes the phase parameter of the clock signal dynamically based on operating conditions. By adjusting the phase shift amount according to the operating voltage level, the system compensates for non-linear delay variations in buffers, maintaining reliable clock distribution even when power consumption is reduced through voltage scaling
2Reliability
If additional buffering is added to clock trees to compensate for delay variations, then clock signal reliability is improved, but device complexity and power requirements increase
Solution Approach 1:
Instead of adding more buffers, the patent changes the phase parameter of the existing clock signal to compensate for delay variations. This approach maintains clock signal reliability by adjusting timing characteristics rather than increasing the number of buffering components, thereby avoiding increased device complexity and power consumption
Solution Approach 2:
The patent extracts the phase adjustment function from the buffer structure itself and implements it separately through a dedicated phase adjustment circuit. This separation allows the existing buffer tree to remain simple while the phase compensation is applied independently, avoiding the need to add additional buffering stages
Data Source
AI summary
Clock phases of clock signals in a dual clock tree are adjusted to compensate for variances in propagation delays of buffers in the clock tree. A first input clock and a second input clock are generated with the second input clock having a phase that is programmably shifted relative to the first input clock when the system is operating at a lowered operating voltage or different temperature, for example. The first and second input clocks are coupled to a dually clocked flip flop, each having a primary latch and a secondary latch. A composite clock signal is generated in response to the first input clock and the second input clock. For example, a first signal is latched in the primary latch in response to the composite clock signal and a second signal is latched in the secondary latch in response to the first input clock signal.