Dual-Clock Feedforward Buffer Circuit for ADC Phase Matching
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Solution Overview
Problem
In time-interleaved sampling systems with multiple ADCs, phase mismatches between sampling clocks due to circuit delays and temperature deviations become significant as input signal frequency increases, affecting system performance.
Innovation Solution
A dual-clock generation circuit incorporating first and second inverter modules with feedforward buffers to compensate and delay clock signals, reducing phase mismatch by adjusting the timing of clock edges, thereby decoupling phase mismatch from initial clock frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If traditional clock generation circuits are used, then the circuit structure is simple, but phase mismatch increases as input signal frequency increases
Solution Approach 1:
The patent applies preliminary action by introducing feedforward buffers that advance the timing of clock signals before they reach the ADCs. The first feedforward buffer transmits the first signal to compensate for the second clock output signal, and the second feedforward buffer transmits the second signal to delay the first clock output signal, thereby pre-correcting phase mismatches before they affect the sampling process
Solution Approach 2:
The patent uses feedforward buffers as intermediary elements between the clock generation circuit and the ADCs. These buffers act as mediators that adjust the timing of clock signals, with the first feedforward buffer compensating the second clock signal and the second feedforward buffer delaying the first clock signal, thereby resolving phase mismatch issues
2Productivity
If sampling rate is increased to improve system performance, then productivity increases, but phase mismatch becomes more significant
Solution Approach 1:
The feedforward buffers perform preliminary timing adjustment on clock signals before they are used for high-rate sampling. By advancing or delaying clock edges in advance through the feedforward paths, the system maintains accurate phase relationships even at increased sampling rates
Solution Approach 2:
The patent implements a feedback mechanism where the output of each inverter module is fed forward to compensate the other clock signal. The first feedforward buffer uses the first signal to compensate the second clock, and the second feedforward buffer uses the second signal to delay the first clock, creating a self-correcting system that maintains phase accuracy
Data Source
AI summary
The present disclosure relates to a dual-clock generation circuit and method and an electronic device, and relates to the technical field of integrated circuits. The dual-clock generation circuit includes: a first inverter module, configured to access a first signal and output a first clock output signal; a second inverter module, configured to access a second signal and output a second clock output signal, where the first signal and the second signal are opposite clock signals; a first feedforward buffer, disposed between an input terminal of the first inverter module and an output terminal of the second inverter module, and configured to transmit the first signal to compensate for the second clock output signal.