Dual-Clock Ramp ADC Circuit for Lower-Power Image Sensing
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Solution Overview
Problem
Analog-to-digital converters (ADCs) in image sensors are a power consumption bottleneck due to their high number of required clock cycles for conversion, which is exacerbated by ramp-based ADCs with limited column circuitry and small die size.
Innovation Solution
The ADC circuit employs two counters with different clock frequencies to reduce the number of clock cycles needed for conversion, using a first counter with a lower frequency for most significant bits and a second counter with a higher frequency for least significant bits, activated at different times to cover only specific voltage ranges, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a single counter with high clock frequency is used for full-resolution conversion, then conversion resolution is maintained, but power consumption increases due to continuous high-frequency counting across the entire voltage range
Solution Approach 1:
The voltage range is segmented into two parts: a first voltage range covered by a first counter with lower clock frequency for major voltage variations, and a second voltage range covered by a second counter with higher clock frequency for fine voltage variations. This segmentation allows each counter to operate at optimal frequency for its specific range, reducing overall power consumption while maintaining full resolution
Solution Approach 2:
The system dynamically switches between two counting modes based on the instantaneous voltage level. When the analog signal is in the first voltage range, the first counter operates; when it transitions to the second voltage range, the second counter takes over. This dynamic adaptation ensures high resolution is only applied when necessary, reducing power consumption during periods when full resolution is not required
2Area of stationary object
If ramp-based ADC with limited column circuitry is used, then die size is reduced, but power consumption bottleneck increases due to high clock cycle requirements
Solution Approach 1:
The conversion process is segmented into two phases using two counters with different clock frequencies. The first counter handles the majority of the conversion at lower frequency, reducing the total number of high-frequency clock cycles required. This maintains the compact ramp-based ADC structure while significantly reducing power consumption
Solution Approach 2:
The system changes the clock frequency parameter dynamically by switching between a lower frequency for the first counter and a higher frequency for the second counter. This parameter change allows the ADC to maintain resolution requirements while reducing the overall clock cycle count and associated power consumption in the limited column circuitry
Data Source
AI summary
An ADC circuit includes a comparator with a first input for receiving an analog signal and with a second input for receiving a ramp signal, a first output of the comparator, a second output of the comparator, a first counter connected to the first output, a second counter connected to the second output, a first clock connected to the first counter, and a second clock connected to the second counter. The first clock provides a first clock signal to the first counter, the second clock provides a second clock signal to the second counter, the first counter is configured to count with the frequency of the first clock signal, the second counter is configured to count with the frequency of the second clock signal. The frequency of the first clock signal is lower than the frequency of the second clock signal.