Two-Reference Clock Redriver for PCIe Phase Jitter Isolation

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Solution Overview

Problem

Current server blade architectures face limitations in storage capacity due to separate reference clocks, which prevent the use of spread-spectrum clocking and lead to phase jitter issues, causing system failures and inefficiencies in high-speed data transfer protocols like PCI-Express.

Innovation Solution

A redriver device with two reference clocks, one common and one low-jitter, is introduced to couple storage blades to server blades, enabling elastic buffer adjustments and clock recovery logic to manage frequency differences and ensure reliable data transfer across non-common clock domains.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a common reference clock is used across all blades, then phase jitter is reduced and spread-spectrum clocking can be supported, but the backplane architecture becomes more complex and costly

Engineering Contradiction:
Improvephase jitterVSAvoidbackplane architecture
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The system divides the clock reference architecture into two segments: a common reference clock domain for the backplane and North Bridge, and separate reference clock domains for individual storage blades. This segmentation allows each domain to operate independently with appropriate clock characteristics while maintaining overall system synchronization through the elastic buffer.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The redriver with elastic buffer acts as an intermediary device between the common reference clock domain (backplane) and separate reference clock domain (storage blade). It mediates the clock domain mismatch by accepting data from either clock domain and translating it to the appropriate domain, enabling communication without requiring a unified clock architecture across the entire system.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of manufacture

If low cost crystal plus clock generator is used, then cost is reduced, but phase jitter increases and spread-spectrum clocking becomes vulnerable

Engineering Contradiction:
ImprovecostVSAvoidphase jitter
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The system applies different clock quality requirements to different locations in the architecture. The common reference clock on the backplane can be lower cost with higher jitter, while the storage blade uses a separate reference clock with lower jitter requirements. The elastic buffer compensates for the quality difference, allowing each component to use the most cost-effective clock source for its specific function.

Inventive Principle:
Principle #3Local quality

3Adaptability or versatility

If separate reference clocks are used on server and storage blades, then cost is reduced and architecture flexibility is improved, but spread-spectrum clocking cannot be supported and phase jitter increases

Engineering Contradiction:
Improvearchitecture flexibilityVSAvoidspread-spectrum clocking support
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The elastic buffer provides dynamic adaptation to clock frequency differences between separate reference clocks. It continuously adjusts its operation to accommodate varying clock rates and jitter characteristics, enabling the system to support spread-spectrum clocking and maintain reliable data transfer even when blades use independent, flexible clock architectures.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS20100315135A1Redriver With Two Reference Clocks And Method Of Operation Thereof
Publication Date: 2010.12.16 HEWLETT PACKARD ENTERPRISE DEV LP
  • US20100315135A1 patent drawing
  • US20100315135A1 patent drawing
  • US20100315135A1 patent drawing

AI summary

A two reference clock architected redriver includes an inbound elastic buffer and an outbound elastic buffer. Data transmitted to and received from a North Bridge uses a common reference clock architecture. Data transmitted to and received from an external blade uses a separate reference clock architecture. The inbound elastic buffer includes an inbound elastic buffer recovered clock domain, an inbound elastic buffer common reference clock domain, and an inbound decoder/descrambler, an inbound scrambler/encoder, and inbound liner shift registers. The outbound elastic buffer includes an outbound elastic buffer common reference clock domain, an outbound elastic buffer low jitter clock domain, and an outbound decoder/descrambler, an outbound scrambler/encoder, and outbound liner shift register.