Dual-Clock Circuit Using Resonant Start-Up for Low-Power Switching
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Solution Overview
Problem
Existing clock circuits in electronic devices face challenges in efficiently conserving power while maintaining the ability to quickly switch to a high-quality clock signal when needed, leading to excessive power consumption due to long start-up times of primary clocks.
Innovation Solution
A clock circuit system that includes a stand-by clock for low-power mode and a primary clock for active mode, utilizing a resonant start-up signal from the stand-by clock to significantly reduce the start-up time of the primary clock, allowing for faster transitions and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the system uses a primary clock to produce a high-quality clock signal, then the clock signal quality is improved, but the start-up time increases leading to excessive power consumption
Solution Approach 1:
The clock system is divided into two separate clock circuits: a primary clock that generates high-quality clock signals and a stand-by clock that generates lower-power clock signals. This segmentation allows the system to use only the necessary clock quality for each operational state, avoiding the continuous power consumption of the primary clock during low-power modes.
Solution Approach 2:
The stand-by clock is kept running in advance during low-power modes to prepare for quick transitions to active mode. By maintaining a ready-to-use clock signal from the stand-by clock, the system can rapidly switch to active mode without the lengthy start-up time required by the primary clock, thus reducing overall power consumption.
2Speed
If the system switches from low-power mode to active mode frequently, then the responsiveness is improved, but the average power consumption increases due to primary clock start-up time
Solution Approach 1:
The stand-by clock performs preliminary action by continuously generating clock signals in low-power mode, preparing the system for rapid transitions to active mode. This preliminary preparation eliminates the need for the primary clock's lengthy start-up sequence, enabling fast mode switching without proportionally increasing power consumption.
Solution Approach 2:
The system employs periodic action by alternating between using the stand-by clock in low-power mode and the primary clock in active mode. This periodic switching strategy allows the system to maintain responsiveness while managing power consumption by only activating the power-intensive primary clock when actually needed.
3Loss of time
If the system uses the stand-by clock signal to start up the primary clock, then the start-up time is reduced, but the system complexity increases
Solution Approach 1:
The system merges the functions of the stand-by clock and primary clock by using the stand-by clock's output signal to initiate the primary clock's operation. This combining of functions allows the stand-by clock to serve dual purposes: providing clock signals during low-power modes and acting as a start-up trigger for the primary clock, thereby reducing start-up time without adding significant complexity.
Solution Approach 2:
The stand-by clock is designed with multi-functionality, serving both as the clock source during low-power modes and as the start-up signal generator for the primary clock. This universal design eliminates the need for separate start-up circuitry, reducing overall system complexity while achieving fast start-up performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The system reduces the start-up time of the primary clock by 2-10 times, enabling the clock circuit to remain in low-power mode more often and consume significantly less power on average, while still providing high-quality clock signals when required.
Implementation Method 1
the system can use a resonant start-up signal from the stand-by clock that oscillates at a resonant frequency of the primary clock to reduce the start-up time of the primary clock
Data Source
AI summary
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a variable quality clock signal to preserve power for electronic devices. According to one aspect, there is provided a system that includes (i) a stand-by clock, configured to produce a stand-by clock signal when the system is in a low-power mode, and (ii) a primary clock, configured to produce a primary clock signal when the system is in an active mode, with the system configured to switch from the low-power mode to the active mode by providing the output of the stand-by clock as a start-up signal to the primary clock.