Dual-Clock SPI Master Controller for High-Speed Flash Access
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Solution Overview
Problem
Existing SPI controllers face limitations in increasing transmission rate in low-frequency clock domains, leading to restricted data throughput and high power consumption due to the maximum clock frequency constraints, which complicates the design of high-speed IO interfaces.
Innovation Solution
A controller in high-speed SPI master mode is designed with a phase locked loop (PLL) providing two clock signals for a low-speed and high-speed clock domain, including a DMA control interface, software interaction interface, interface clock generation unit, data readback calibration unit, and pin delay control unit, with asynchronous FIFO data buffer units and a compensation circuit to optimize timing control and reduce delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the clock frequency is increased to achieve faster read/write speed, then the transmission rate is improved, but the power consumption and area costs of the controller increase excessively
Solution Approach 1:
The controller is divided into two separate clock domains: a low-speed clock domain for general control functions and a high-speed clock domain specifically for SPI data transmission. This segmentation allows the SPI interface to operate at high speed (improving transmission rate) while the rest of the controller operates at lower speed (reducing overall power consumption and area costs).
Solution Approach 2:
The high-speed clock domain is created with dedicated resources (interface clock generation unit, data readback calibration unit, receiving/sending control units) specifically for SPI communication. This local quality enhancement ensures high transmission rate only where needed (SPI interface) rather than throughout the entire controller, optimizing the balance between speed and power consumption.
2Speed
If the clock frequency is increased to achieve faster read/write speed, then the transmission rate is improved, but the area costs of the controller increase excessively
Solution Approach 1:
The controller architecture segments the high-speed SPI interface from the low-speed control logic into separate clock domains. This allows the high-speed portion to occupy only the necessary area for SPI operations, while the rest of the controller uses lower-speed, smaller-area components, thereby reducing total chip area while maintaining high transmission rate.
Solution Approach 2:
High-speed resources (interface clock generation unit, data readback calibration unit, receiving/sending control units) are localized only to the SPI interface section where high transmission rate is required. Other controller functions operate in the low-speed domain with smaller area requirements, optimizing the area-speed tradeoff.
3Speed
If the clock frequency is increased to achieve faster read/write speed, then the transmission rate is improved, but the difficulty in designing a high-speed IO interface increases
Solution Approach 1:
By segmenting the controller into low-speed and high-speed clock domains, the design complexity of high-speed IO interface is isolated to a specific module (high-speed clock domain). This segmentation allows specialized design techniques to be applied only where needed, rather than throughout the entire controller, making the high-speed interface more manageable and easier to design.
Solution Approach 2:
The interface clock generation unit acts as an intermediary between the PLL and the SPI interface, providing frequency division and timing control. The data readback calibration unit serves as another intermediary to synchronize data sampling with the high-speed clock. These intermediary components simplify the overall design by managing the complexity of high-speed timing and synchronization in a modular fashion.
4Productivity
If data transmission efficiency is improved by optimizing data access, then the throughput is increased, but the transmission rate in low-frequency clock domain shows no obvious improvement
Solution Approach 1:
The controller segments data transmission functions into a dedicated high-speed clock domain with specialized units (interface clock generation unit, data readback calibration unit, receiving/sending control units). This segmentation enables the SPI interface to achieve high transmission rates independent of the low-speed clock domain, resolving the limitation where data optimization alone could not improve transmission rate in low-frequency domains.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively increases the transmission rate by isolating clock domains, reducing delays, and optimizing timing control, allowing stable operation at high speeds, such as 120 MHz, while minimizing power consumption and improving startup times, especially in SPI flash applications.
Implementation Method 1
clock signals are provided by a phase locked loop (PLL), and the entire controller includes: a low-speed clock domain... and a high-speed clock domain... the PLL provides two main clock signals by different clock frequency dividers
Data Source
AI summary
In view of defects in the prior art, the present disclosure provides a controller in a high-speed serial peripheral interface (SPI) master mode, where clock signals are provided by a phase locked loop (PLL), and the entire controller includes: a low-speed clock domain and a high-speed clock domain, where the PLL provides two main clock signals by different clock frequency dividers, provides a low-speed clock signal to the low-speed clock domain, and provides a high-speed source clock signal to the high-speed clock domain. By such technical solutions in the present disclosure, functions of different clock domains are divided through asynchronization of a high-speed SPI controller, and the function of a high-speed SPI flash access is implemented, thereby saving a read/write time. Especially in an application scenario of an SPI flash boot, the controller can greatly optimize a startup time.