Dual-Clock Timing Calibration for eDRX Energy Efficiency
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Solution Overview
Problem
Current wireless communication systems, particularly in extended discontinuous reception (eDRX) mode, face challenges in optimizing timing calibration to balance energy consumption and clock accuracy, leading to inefficiencies in battery life for IoT devices.
Innovation Solution
The implementation of a dual-clock system where a low-power, high-frequency-error clock is used during sleep states and a high-power, low-frequency-error clock is used for calibration, with the selection based on eDRX cycle length and calibration frequency to minimize energy consumption while maintaining accurate timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a high-precision clock is used continuously for timing during eDRX cycles, then timing accuracy is improved, but energy consumption increases
Solution Approach 1:
The patent segments the timing function into two parts: a low-power clock handles timing during sleep states, while a high-precision clock is activated only during calibration periods. This segmentation allows the system to maintain timing accuracy requirements only when necessary, rather than continuously operating the high-precision clock.
Solution Approach 2:
The high-precision clock operates periodically rather than continuously, being activated at specific calibration intervals within the eDRX cycle. This periodic operation maintains timing accuracy through regular calibration while minimizing energy consumption by keeping the high-precision clock dormant during extended sleep periods.
2Use of energy by moving object
If a low-power clock is used during sleep states, then energy consumption is reduced, but timing accuracy deteriorates
Solution Approach 1:
The low-power clock serves as an intermediary timing source during sleep states, providing sufficient timing functionality for basic operations. The high-precision clock acts as a periodic calibrator that corrects accumulated timing errors, allowing the low-power clock to operate with relaxed accuracy requirements during sleep while maintaining overall system timing accuracy through periodic intervention.
Solution Approach 2:
The system changes the operational parameters of the clocks dynamically: during sleep states, the low-power clock operates with higher frequency error tolerance to minimize energy consumption; during calibration periods, the high-precision clock activates to reset and correct timing parameters, ensuring long-term timing accuracy is maintained despite parameter variations during sleep.
3Measurement precision
If calibration frequency is increased to maintain timing accuracy, then timing precision is improved, but energy consumption increases
Solution Approach 1:
Instead of continuously calibrating the timing system, the patent applies partial calibration action at optimized intervals within the eDRX cycle. This partial calibration approach provides sufficient timing accuracy for the application requirements while avoiding excessive calibration operations that would unnecessarily increase energy consumption.
Solution Approach 2:
The calibration mechanism serves multiple functions: it corrects timing drift, synchronizes the low-power clock with network timing, and validates system operation. By consolidating these functions into a single periodic calibration event, the system achieves comprehensive timing management without requiring multiple separate calibration operations, thereby reducing overall energy consumption.
Data Source
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AI summary
Methods, systems, and devices for wireless communication in a user equipment (UE) are described in which a cycle duration of an extended discontinuous reception (eDRX) cycle is determined. The UE enters a sleep state of the eDRX cycle and, based on the determination of the cycle duration, uses a first clock as a timer during the sleep state and uses a second clock as a timing calibrator during the sleep state. The first clock may have a lower power consumption and a higher frequency error, and the second clock may have a higher power consumption and a lower frequency error.