Dual Clocking Memory Device Reduces Read Latency

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Solution Overview

Problem

Semiconductor memory devices experience increased read data latency due to the generation of redundant parity bits through exclusive OR operations, which are necessary for error correction in systematic codes, leading to higher channel bit error rates as operating speeds increase.

Innovation Solution

A dual clocking method is employed in the memory device, where a first read pulse is used to output original data in series, and a second delayed read pulse is used to generate and output CRC bits, allowing for separate clock signals for original data and redundant parity bits, thereby reducing latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If redundant parity bits are generated using logic circuits for exclusive OR operations, then error correction capability is improved, but read data latency increases significantly

Engineering Contradiction:

Improveerror correction capabilityVSAvoidread data latency

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent divides the code generation process into two separate operations: original data output and CRC code generation. By using separate read pulses (first read pulse for data, second delayed read pulse for CRC), the system segments the latency-prone exclusive OR operation from the data output process, allowing data to be read without waiting for parity bit generation.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The CRC generating unit is configured to generate CRC codes in advance using the delayed read pulse before the data output is completed. This preliminary generation of parity bits eliminates the need to wait for real-time calculation during data readout, thereby reducing overall read data latency while maintaining error correction functionality.

Inventive Principle:

Principle #10Preliminary action

2Productivity

If operating speeds of semiconductor memory devices increase, then productivity is improved, but channel bit error rate increases

Engineering Contradiction:

Improveoperating speedVSAvoidchannel bit error rate

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent implements a feedback mechanism where the CRC generating unit continuously monitors and generates parity bits based on the read data. This feedback loop ensures that even at higher operating speeds where errors may occur, the system can detect and correct channel bit errors through the systematic code, maintaining reliability without sacrificing speed.

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS8046665B2Memory device employing dual clocking for generating systematic code and method thereof

Publication Date: 2011.10.25 SAMSUNG ELECTRONICS CO LTD

AI summary

A memory device may include a memory core block, a data patch unit, a Cyclic Redundancy Check (CRC) generating unit, and/or a serializer. The data patch unit may be configured to patch parallel data read from the memory core block in response to a first read pulse. The CRC generating unit may be configured to generate the CRC code based on the parallel data in response to a second read pulse, the second read pulse delayed by a period of time from if the first read pulse is generated. The serializer may be configured to convert the parallel data to serial data in response to the first read pulse, and/or arrange the CRC code in a order for a number of bits of the serial data to generate a systematic code.