Dual Column Address Decoders for DRAM Stability
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Solution Overview
Problem
The column addressing operation in memory devices, such as DRAM, is destabilized due to differences in signal characteristics and timings across the large physical size of the memory bank, leading to unstable data input/output operations.
Innovation Solution
The implementation of a memory device with dual strobe transfer paths and latch circuits synchronized with strobe signals to generate column select signals, ensuring equal signal strengths and timings across the memory bank, thereby stabilizing the column addressing operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single column decoder is used in a large memory bank, then device complexity is reduced, but signal characteristics and timings become unstable across different regions of the memory bank
Solution Approach 1:
The memory bank is divided into two regions (first memory bank and second memory bank), each with its own column decoder (first column decoder and second column decoder). This segmentation allows each decoder to serve a specific region, reducing signal degradation and timing variations across the entire memory bank while maintaining overall system functionality.
Solution Approach 2:
Each region of the memory bank is equipped with a dedicated column decoder, allowing local optimization of signal characteristics and timing for each specific region. This ensures that signal strength and timing are appropriate for the local distance from the decoder, improving overall addressing stability.
2Productivity
If the memory bank size is increased to improve capacity, then productivity is improved, but signal timing differences across the bank increase causing instability
Solution Approach 1:
The large memory bank is segmented into multiple smaller regions, each with its own column decoder. This allows the memory bank to maintain large total capacity while ensuring that no single decoder has to drive signals across the entire large distance, thereby maintaining signal integrity and timing stability in each region.
3Productivity
If operating speed is increased to improve productivity, then productivity is improved, but timing differences across the memory bank cause instability
Solution Approach 1:
By dividing the memory bank into regions with dedicated decoders, the maximum signal travel distance is reduced. This allows higher operating speeds to be achieved because the timing constraints for each regional decoder are less severe than for a single decoder serving the entire large bank.
Data Source
AI summary
A memory device includes a memory bank; a first latch circuit positioned at the one side of the memory bank, for latching a first column address in synchronization with a first strobe signal; a second latch circuit positioned at the other side of the memory bank, for latching a second column address in synchronization with a second strobe signal; a first column decoder positioned at the one side of the memory bank, for generating first column select signals in synchronization with the first strobe signal and the first column address; and a second column decoder positioned at the other side of the memory bank, for generating second column select signals in synchronization with the second strobe signal and the second column address.