Dual-Column CCD Readout Circuit for High-Speed Low-Noise Inspection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current CCD image sensors face challenges in achieving high sensitivity and high-speed operation due to limitations in read noise reduction, particularly at small pixel sizes, and the practicality of column-parallel readout architectures.
Innovation Solution
The development of a dual-column-parallel CCD image sensor with a novel readout circuit that coordinates the high-speed transfer of charges from pairs of adjacent pixel columns to a shared floating diffusion for readout by a single amplifier, addressing issues of high switching currents, read noise, and amplifier space constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional serial-readout architecture is used to increase readout speed, then inspection speed is improved, but read noise increases significantly
Solution Approach 1:
The patent divides the pixel array into multiple independent column-parallel readout channels, each with its own amplifier. This segmentation allows simultaneous readout of multiple columns, achieving high-speed inspection while keeping the pixel clock rate low (2-4 MHz) to minimize read noise in each channel.
Solution Approach 2:
The patent transitions from one-dimensional serial readout to two-dimensional column-parallel readout by adding the column dimension as an independent readout path. This dimensional change enables concurrent readout of multiple columns without increasing the clock rate of individual channels, thus maintaining low read noise while achieving high overall inspection speed.
2Productivity
If column-parallel readout architecture is implemented for high-speed inspection, then inspection speed is improved, but amplifier space requirements increase
Solution Approach 1:
The patent merges multiple column outputs into shared summing gates that combine signals from multiple columns before amplification. This merging reduces the number of amplifiers needed while maintaining column-parallel readout capabilities, thereby reducing the amplifier space requirement while preserving high inspection speed.
Solution Approach 2:
The summing gates serve multiple functions: they receive signals from multiple columns, perform signal combining, and drive shared amplifiers. This multi-functionality allows the system to achieve high-speed inspection with fewer amplifiers, reducing the overall amplifier space required in the sensor design.
3Object-affected harmful factors
If pixel binning is used to reduce read noise, then sensitivity is improved, but spatial resolution decreases
Solution Approach 1:
The patent maintains separate readout channels for individual pixels without binning, preserving spatial resolution. By implementing column-parallel readout with low pixel clock rates, the system achieves low read noise without combining signals from multiple pixels, thus maintaining full spatial resolution while improving sensitivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables the production of CCD sensors with small column pitches suitable for high-speed semiconductor inspection applications, achieving low noise and high-speed readout operations while maintaining high sensitivity.
Implementation Method 1
The photons incident on an image sensor carry time-dependent fluctuations in the photon flux
Implementation Method 2
two pairs of transfer gates, a common summing gate, a floating diffusion, and an amplifier per two columns. Each column of the CCD pixels is terminated by a pair of transfer gates
Implementation Method 3
an output circuit including a single amplifier configured to generate output voltage signals based on the image charges transferred from the associated pair of columns
Data Source
Figure 1
Figure 2A~2B
Figure 3
AI summary
A dual-column-parallel image CCD sensor utilizes a dual-column-parallel readout circuit including two pairs of cross-connected transfer gates to alternately transfer pixel data (charges) from a pair of adjacent pixel columns to a shared output circuit at high speed with low noise. Charges transferred along the two adjacent pixel columns at a line clock rate are alternately passed by the transfer gates to a summing gate that is operated at twice the line clock rate to pass the image charges to the shared output circuit. A symmetrical Y-shaped diffusion is utilized in one embodiment to merge the image charges from the two pixel columns. A method of driving the dual-column-parallel CCD sensor with line clock synchronization is also described. A method of inspecting a sample using the dual-column-parallel CCD sensor is also described.