Dual-Column-Parallel CCD Sensor Readout Circuit
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Solution Overview
Problem
Current CCD image sensors face challenges in achieving high-sensitivity and high-speed operation due to high read noise associated with serial readout architectures and space constraints for amplifiers in small column pitch designs.
Innovation Solution
The development of dual-column-parallel CCD image sensors with a novel readout circuit that coordinates the high-speed transfer of charges from pairs of adjacent pixel columns to a shared floating diffusion for readout by a single amplifier, avoiding high switching currents and read noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If serial-readout architecture is used to reduce device complexity, then amplifier quantity is reduced, but readout speed decreases and read noise increases
Solution Approach 1:
The patent divides the pixel array into multiple independent column groups, each with its own readout path containing an amplifier. This segmentation allows parallel readout of multiple columns simultaneously, increasing readout speed while maintaining a manageable number of amplifiers compared to fully parallel architecture.
Solution Approach 2:
The patent introduces a temporal dimension to the readout process by implementing sequential activation of column groups. Different column groups are read out at different time intervals, allowing the system to achieve high effective readout speed without requiring all amplifiers to operate simultaneously, thus reducing peak power consumption and heat generation.
2Speed
If column-parallel readout architecture is used to increase readout speed, then amplifier quantity increases, but space constraints prevent implementation in small column pitch designs
Solution Approach 1:
The patent segments the pixel array into column groups where each group shares a readout path. This reduces the total number of amplifiers needed compared to fully column-parallel architecture, while still providing parallel readout capability within each group, making it feasible for small column pitch designs with limited space.
Solution Approach 2:
The patent merges multiple columns into column groups that share common readout paths and amplifiers. By combining several columns under a single readout path, the system reduces the total amplifier count and associated space requirements, enabling implementation in compact sensor designs with small column pitches.
3Productivity
If high pixel clock rate is used to maintain inspection speed with smaller pixel sizes, then readout speed increases, but read noise increases
Solution Approach 1:
The patent divides the pixel array into multiple column groups with independent readout paths, enabling simultaneous readout of multiple columns. This parallel processing approach maintains high inspection speed without requiring excessively high pixel clock rates, thereby reducing read noise generated at high frequencies.
Solution Approach 2:
The patent implements dynamic clock rate adjustment for different column groups, allowing optimization of the pixel clock rate for each group based on its specific requirements. This dynamic approach enables maintaining high inspection speed while minimizing read noise by using the lowest necessary clock rates for each column group.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables CCD sensors with small column pitches suitable for high-speed semiconductor inspection applications, achieving high-sensitivity and low-noise operation while maintaining reasonable clock rates.
Implementation Method 1
two rows of transfer gates respectively transfer image charges from the associated pair of columns to the summing gate
Implementation Method 2
a summing gate coupled to alternately receive and sum the image charges passed from the transfer gates
Implementation Method 3
an output circuit including a single amplifier configured to generate output voltage signals based on the image charges transferred from the associated pair of columns
Data Source
Figure 1
Figure 2A~2B
Figure 3
AI summary
A dual-column-parallel image CCD sensor utilizes a dual-column-parallel readout circuit including two pairs of cross-connected transfer gates to alternately transfer pixel data (charges) from a pair of adjacent pixel columns to a shared output circuit at high speed with low noise. Charges transferred along the two adjacent pixel columns at a line clock rate are alternately passed by the transfer gates to a summing gate that is operated at twice the line clock rate to pass the image charges to the shared output circuit. A symmetrical Y-shaped diffusion is utilized in one embodiment to merge the image charges from the two pixel columns. A method of driving the dual-column-parallel CCD sensor with line clock synchronization is also described. A method of inspecting a sample using the dual-column-parallel CCD sensor is also described.