DRAM Memory Layout With Dual Column Decoders for Read Accuracy
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Solution Overview
Problem
Existing Dynamic Random Access Memory (DRAM) systems experience read errors due to varying time consumption when reading data from different positions in the memory cell array, leading to reduced read accuracy and performance.
Innovation Solution
The implementation of a first and second column decoder, positioned on opposite sides of the memory cell array, allows for simultaneous and consistent read operations by directing data to a read amplifier, ensuring equal time consumption for data transmission regardless of the memory cell's position.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single column decoder is used for read operations, then the device complexity is reduced, but the read accuracy deteriorates due to varying data transmission times from different memory cell positions
Solution Approach 1:
The column decoder is divided into two separate decoders: a first column decoder for write operations and a second column decoder for read operations. This segmentation allows each decoder to be optimized for its specific function and positioned to minimize signal transmission distance to memory cells at different locations, thereby equalizing read times and improving read accuracy without requiring a single overly complex decoder
2Reliability
If the read amplifier and second column decoder are positioned on the same side of the memory cell array, then the device layout is simplified, but the read errors increase due to unequal data transmission times from memory cells at different positions
Solution Approach 1:
The read amplifier and second column decoder are positioned on opposite sides of the memory cell array, utilizing the spatial dimension effectively. This opposite-side configuration creates two symmetrical signal transmission paths, allowing memory cells at different positions to have approximately equal transmission distances to the read amplifier, thereby equalizing read times and reducing read errors while managing layout space
Data Source
AI summary
A memory includes: a memory cell array; a first column decoder, coupled to the memory cell array and configured to perform a write operation on the memory cell array; a second column decoder, coupled to the memory cell array and configured to perform a read operation on the memory cell array; and a read amplifier, the read amplifier and the second column decoder being located on two opposite sides of the memory cell array, the read amplifier being coupled to the memory cell array and configured to receive read data information output by the memory cell array based on the read operation. The read amplifier, the first column decoder, the memory cell array and the second column decoder are arranged in a first direction, and the first column decoder and the second column decoder are located on two opposite sides of the memory cell array.