Dual Command State Machine for SPI DTR DPD Reliability
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Solution Overview
Problem
Serial Peripheral Interface (SPI) devices face challenges in reliably processing commands at higher frequencies while in Double Transfer Rate (DTR) mode and Deep Power Down (DPD) mode due to unreliable clock frequency-doubling circuits, which become less reliable when internal voltage references are disabled for power savings.
Innovation Solution
The implementation of a dual command state machine architecture, where a legacy CSM operates on one clock edge in standard modes and a DTR+DPD CSM processes commands on both clock edges, ensuring reliable operation in DTR and DPD modes by selectively enabling the appropriate CSM based on operational characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If clock frequency-doubling circuits are used to achieve higher DTR frequencies, then data communication rate is improved, but reliability deteriorates when internal voltage references are disabled for power savings
Solution Approach 1:
The patent divides the single command state machine into two separate CSMs: a legacy CSM that operates on one clock edge and a DTR+DPD CSM that operates on both clock edges. This segmentation allows each CSM to be optimized for specific operating conditions, with the DTR+DPD CSM handling high-frequency DTR mode operations reliably even when voltage references are disabled for power savings.
Solution Approach 2:
The patent changes the operational parameters of the command state machines by enabling the DTR+DPD CSM to process commands on both rising and falling clock edges, whereas the legacy CSM processes commands on only one edge. This parameter change allows the system to maintain reliable command processing at higher frequencies in DTR mode without requiring continuous operation of internal voltage references.
2Use of energy by moving object
If internal voltage references are disabled for power savings in DPD mode, then power consumption is reduced, but clock frequency-doubling reliability deteriorates
Solution Approach 1:
The patent segments the command processing function into two independent CSMs, allowing the DTR+DPD CSM to handle high-frequency operations in DPD mode without requiring the internal voltage references that the legacy CSM would need. This enables the system to disable voltage references for power savings while maintaining reliable command processing through the DTR+DPD CSM.
Solution Approach 2:
The DTR+DPD CSM acts as an intermediary that enables reliable command processing in DTR mode during DPD operation, even when internal voltage references are disabled. This intermediary CSM bridges the gap between power-saving requirements and the need for reliable high-frequency command processing.
3Device complexity
If a single CSM processes commands on one clock edge, then device complexity is reduced, but productivity deteriorates in DTR mode where both edges should be utilized
Solution Approach 1:
The patent segments command processing into two specialized CSMs: one for legacy single-edge operation and one for DTR dual-edge operation. Although this increases the number of CSMs, each CSM remains relatively simple in structure, and the segmentation enables full utilization of both clock edges in DTR mode, thereby improving productivity without excessive complexity increase.
Solution Approach 2:
The DTR+DPD CSM is designed with multi-functionality to handle both DTR mode operations (processing commands on both clock edges) and DPD mode operations (maintaining reliability when voltage references are disabled). This universal CSM can adapt to different operating conditions, improving overall system productivity across multiple modes.
Data Source
AI summary
Serial peripheral interfaces and methods of operating the same are provided. An apparatus can have a serial peripheral interface (SPI) including a first command state machine (CSM), and a second CSM.