Dual-Compact Expansion Card Offloads CPU Tasks
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Solution Overview
Problem
The demand for efficient execution of complex computational tasks like video transcoding and artificial intelligence operations is increasing, but traditional data center servers are expensive to deploy and maintain, and edge servers often lack the necessary resources due to physical and power constraints, making it inefficient to scale for high-demand computing tasks.
Innovation Solution
The use of dual-compact-form-factor expansion cards with application-specific hardware circuitry and multiple pinouts that conform to compact specifications, such as M.2, U.2, or mSATA, to offload computing tasks from central processing units and provide hardware acceleration, allowing for more efficient and scalable performance of tasks like AI inference and video transcoding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If traditional domain controllers are deployed to handle complex computational tasks, then computing power is improved, but deployment cost and maintenance expense increase
Solution Approach 1:
The patent segments the computing system into general-purpose domain controllers and specialized hardware accelerator cards. The hardware accelerators are separate, modular components that can be independently deployed and configured to handle specific computational tasks (video transcoding, AI operations) without requiring full domain controller deployments, thereby reducing costs while maintaining computing power.
Solution Approach 2:
The patent introduces hardware accelerator cards as intermediary components between the domain controller and computational tasks. These accelerators offload specific processing workloads from the domain controller, providing enhanced computing power for complex tasks while keeping the domain controller's role and deployment costs manageable.
2Adaptability or versatility
If edge servers are used to service high-growth points-of-presence, then scalability is improved, but physical space and power constraints worsen
Solution Approach 1:
The patent merges multiple functionality into a single edge server by integrating hardware accelerator cards into the existing server infrastructure. This combination allows the edge server to handle both general operations and complex computational tasks (video transcoding, AI) within the same physical space, improving scalability without requiring additional dedicated hardware for each function.
Solution Approach 2:
The patent adds computational capability in a new dimension by incorporating hardware accelerators that provide specialized processing power without proportionally increasing physical space requirements. The accelerators operate in parallel with the existing server architecture, effectively adding computing capacity without linearly expanding the physical footprint.
3Productivity
If traditional expansion cards are used for hardware acceleration, then computing task offloading is improved, but device complexity and deployment cost increase
Solution Approach 1:
The patent designs hardware accelerator cards with universal interfaces and standardized form factors that can be deployed across multiple device types and configurations. The accelerators support various computational workloads (video transcoding, AI operations, cryptography) through a single platform, reducing the need for multiple specialized devices and simplifying the overall system complexity.
Solution Approach 2:
The patent utilizes parameter changes in the hardware accelerator design, specifically using compact form factors and standardized interfaces, to reduce device complexity. By changing physical parameters (size, interface standards) while maintaining functional capabilities, the accelerators become easier to integrate and deploy without increasing overall system complexity.
Data Source
AI summary
A disclosed expansion card may include a printed circuit board and a hardware accelerator. The hardware accelerator may be disposed on the printed circuit board and may include application-specific hardware circuitry designed to perform a computing task. The hardware accelerator may offload a portion of the computing task from a central processing unit of a computing device by executing, via the application-specific hardware circuitry, the portion of the computing task. The expansion card may also include an edge connector, disposed on a connecting edge of the printed circuit board, that may couple the hardware accelerator to the central processing unit via a computing bus. The edge connector may also include a primary pinout and a secondary pinout that may each conform to a compact pinout specification that may be more compact than a pinout specification defined for the computing bus. Various other systems and methods are also disclosed.