Dual-Comparator ADC Architecture for Low-Power Accurate Conversion
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Solution Overview
Problem
Analog-to-digital converters (ADCs) consume a large amount of power during signal conversion, which is inefficient and not effectively addressed by existing technologies.
Innovation Solution
The proposed ADC employs a dual-comparator architecture with asynchronous clock signals and control logic to reduce power consumption by using a coarse ADC for determining upper bits and a fine ADC for determining lower bits, with capacitors and switches adjusting reference signals to optimize conversion efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a conventional ADC architecture is used, then conversion accuracy is maintained, but power consumption increases
Solution Approach 1:
The ADC is divided into two independent conversion paths: a coarse ADC for upper bits and a fine ADC for lower bits. Each path operates with its own comparator and capacitor array, allowing selective activation based on power requirements while maintaining overall conversion accuracy through concatenation of results.
Solution Approach 2:
The system dynamically selects which ADC path to activate based on power availability and conversion requirements. The coarse ADC can operate independently for low-power modes, while the fine ADC activates when higher precision is needed, enabling adaptive power management without sacrificing accuracy when required.
2Speed
If a single comparator is used, then device complexity is reduced, but conversion speed decreases
Solution Approach 1:
The comparison function is segmented into two independent comparators operating in parallel but with different clock domains. The first comparator handles coarse comparison for upper bits while the second comparator handles fine comparison for lower bits, allowing simultaneous operation without interference and achieving faster overall conversion.
Solution Approach 2:
The two comparators operate with different periodic clock signals - the first comparator uses a faster clock for coarse comparison while the second comparator uses a slower clock for fine comparison. This periodic operation with different frequencies allows the system to achieve high-speed coarse conversion followed by precision fine conversion.
3Use of energy by moving object
If asynchronous clock signals are used, then power consumption is reduced, but control complexity increases
Solution Approach 1:
The control system is segmented into two independent control logic units, each managing one comparator and its associated capacitor array with dedicated asynchronous clocks. This segmentation isolates control complexity into manageable sections that can operate independently, reducing the overall control burden while enabling power-efficient asynchronous operation.
Solution Approach 2:
Each comparator-capacitor array pair is self-contained with its own control logic and clock signal, allowing autonomous operation. The first comparison result automatically triggers the second comparison sequence, creating a self-managing system where control signals propagate naturally through the conversion pipeline without centralized coordination overhead.
Data Source
AI summary
An analog-to-digital converter (ADC) includes a first comparator configured to generate a first comparison signal on a basis of a first asynchronous clock signal generated from a sampling clock signal, and a second comparator configured to generate a second comparison signal on a basis of a second asynchronous clock signal generated by a first comparison operation completion signal. The ADC includes a first control logic configured to output a first control signal on a basis of the first comparison signal and a second control logic configured to output a second control signal on a basis of the second comparison signal. The ADC includes a first reference signal adjusting circuit configured to adjust a first reference signal on a basis of the first control signal and a second reference signal adjusting circuit configured to adjust a second reference signal on a basis of the second control signal.