Dual-Comparator ADC Circuit for Fast Low-Power Image Sensing
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Solution Overview
Problem
Current single slope analog-to-digital converters (ADCs) in CMOS image sensors face challenges in meeting the demands of high resolution, high speed imaging, and low power consumption, particularly as image resolution increases and power consumption from counters becomes a concern.
Innovation Solution
An analog-to-digital conversion circuit utilizing two comparators and a counter circuit that switches between two clock signals of different frequencies based on the comparison of an analog signal with a ramp signal and a ramp signal plus a predetermined offset, allowing for coarse and fine counting to optimize conversion speed and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single slope ADC is used to meet small pixel size requirements, then device complexity is reduced, but conversion speed becomes insufficient for high speed imaging
Solution Approach 1:
The conversion process is segmented into two phases: a first conversion phase using a first ADC with first clock frequency, and a second conversion phase using a second ADC with second clock frequency. This segmentation allows each phase to be optimized for different requirements - the first phase handles initial conversion with lower power consumption, while the second phase provides high-speed conversion when needed, thereby resolving the contradiction between device complexity and conversion speed.
Solution Approach 2:
The system dynamically switches between different ADC configurations and clock frequencies based on imaging requirements. The control circuit adjusts the operating mode between first and second conversion phases, and dynamically selects between first and second clock signals. This dynamic adaptation enables the system to achieve high conversion speed when needed while maintaining low complexity architecture during normal operation.
2Measurement precision
If image resolution is increased to meet high resolution imaging demands, then measurement precision is improved, but conversion speed of single slope ADC cannot meet high speed imaging requirements
Solution Approach 1:
The system changes operating parameters by switching between different clock frequencies (first clock frequency and second clock frequency) and different ADC configurations. During the first conversion phase, the system operates with parameters optimized for precision, while during the second conversion phase, parameters are adjusted to prioritize speed. This parameter changes approach allows the system to achieve both high resolution and high speed imaging requirements.
3Device complexity
If counter of single slope ADC is used for conversion, then device complexity is reduced, but power consumption increases
Solution Approach 1:
The system employs periodic action by alternating between first and second conversion phases. The first conversion phase uses lower power consumption mode with first clock signal, while the second conversion phase uses higher speed mode with second clock signal. This periodic switching between different operating modes reduces overall power consumption compared to continuously operating in high-speed mode, while still meeting high speed imaging requirements when necessary.
Solution Approach 2:
The control circuit dynamically adjusts the operating state between different conversion phases and clock frequencies based on actual imaging needs. By dynamically switching to lower frequency operation during phases that don't require maximum speed, the system significantly reduces power consumption while maintaining the capability to switch to high-speed mode when high resolution imaging is required.
Data Source
AI summary
An analog-to-digital conversion circuit includes a first comparator, a second comparator and a counter circuit. The first comparator compares an analog signal with a ramp signal. The second comparator compares the analog signal with the ramp signal plus a predetermined offset. When a signal level of the ramp signal is less than a signal level of the analog signal, the counter circuit counts a number of clock cycles of a first clock signal to generate a first portion of a digital signal. When the signal level of the ramp signal plus the predetermined offset is greater than the signal level of the analog signal, the counter circuit counts a number of clock cycles of a second clock signal to generate a second portion of the digital signal. A frequency of the first clock signal is less than a frequency of the second clock signal.