Dual-Comparator PLL for Low-Noise Beamforming Phase Control
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Solution Overview
Problem
Phase locked loops (PLLs) in wireless systems face stringent phase noise requirements due to closer sub-carrier spacing in 5G millimeter wave communications, necessitating accurate phase shifts for beamforming, while also needing to be programmable for different frequency channels and bands, all while minimizing power consumption and chip area.
Innovation Solution
A phase locked loop arrangement that includes a digital loop filter providing a digital control word to a digital controlled oscillator, with a frequency divider generating delayed feedback signals for comparator paths to achieve precise phase control, reducing transistor matching requirements and area consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional PLL is used to generate oscillator signals for beamforming, then the system can operate at millimeter wave frequencies, but the phase noise becomes excessive due to stringent requirements from closer sub-carrier spacing
Solution Approach 1:
The feedback signal path is segmented into multiple paths with different delay elements. Each comparator path processes feedback signals with specific delay characteristics, allowing the system to select optimal phase comparison paths for different sub-carrier spacing configurations, thereby reducing phase noise while maintaining adaptability
Solution Approach 2:
The system dynamically adjusts the delay elements in the feedback paths based on operating conditions. The delay elements can be reconfigured to provide different phase shifts, enabling the PLL to adapt to varying sub-carrier spacing requirements while maintaining low phase noise performance across different operational modes
2Measurement precision
If the phase of the oscillator signal is made programmable for beamforming control, then accurate beam direction control is achieved, but the circuit complexity and chip area increase
Solution Approach 1:
The dual-comparator architecture with configurable delay elements serves multiple functions: it provides phase measurement, frequency measurement, and programmable phase shifting all within the same PLL structure. This multi-functionality reduces the need for separate circuit blocks, thereby controlling chip area while achieving accurate phase control
Solution Approach 2:
The system achieves programmable phase control by changing the delay parameters in the feedback paths rather than using complex phase shifters. By adjusting the delay element configurations, different phase shifts are obtained, providing accurate beamforming control with simpler circuitry
3Adaptability or versatility
If the PLL is designed to support multiple frequency channels and bands, then the wireless device becomes more versatile, but the power consumption increases
Solution Approach 1:
The delay elements in the feedback paths are designed to be dynamically reconfigurable, allowing the same PLL circuit to operate across multiple frequency channels and bands. This dynamic reconfiguration capability eliminates the need for multiple dedicated PLL circuits, thereby reducing overall power consumption while maintaining frequency versatility
Solution Approach 2:
The PLL architecture with configurable delay elements and dual comparator paths serves as a universal frequency synthesis solution that can be programmed for different frequency channels and bands. This single multi-functional circuit replaces what would otherwise require multiple dedicated circuits, reducing total power consumption
4Measurement precision
If stringent phase noise requirements are imposed on the PLL output for closer sub-carrier spacing, then OFDM modulation performance is maintained, but the beamforming capability is compromised due to limited phase adjustment range
Solution Approach 1:
The feedback path is divided into multiple segmented paths with different delay elements. By selectively activating different segments and adjusting their delay characteristics, the system can simultaneously maintain low phase noise for OFDM while providing sufficient phase shift range for beamforming operations
Solution Approach 2:
The delay elements are dynamically adjustable, allowing the system to optimize the phase noise performance for OFDM modulation while simultaneously providing the necessary phase shift range for beamforming. The dynamic reconfiguration enables the PLL to adapt to different operational requirements without compromising either performance metric
Data Source
AI summary
A phase locked loop, for a particularly in a beamforming system comprises a digital loop filter to provide a digital control word to a controllable oscillator; a frequency divider configured to provide a first feedback signal and a second feedback signal in response to an oscillator signal, the second feedback signal delayed with respect to the first feedback signal; a first comparator path configured to receive the first feedback signal and a second comparator path configured to receive the second feedback signal, each of the first and second comparator path configured to provide a respective phase delay signal to the digital loop filter in response to a respective adjustment signal and a phase deviation between a common reference signal and the respective feedback signal.