Dual-Comparator SAR ADC for Speed and Power Efficiency
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Solution Overview
Problem
Existing SAR ADCs face challenges in achieving both speed and power efficiency in converting high-speed data signals due to the capacitive load from a large number of storage circuits coupled to comparators, which degrades operation speed and power efficiency.
Innovation Solution
A SAR ADC design that utilizes two comparators with different detection speeds and sensitivities, where a faster comparator determines most significant bits and a more sensitive comparator determines least significant bits, with reduced capacitive loads by separating storage circuits for each comparator, allowing efficient state determination of input voltage bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a large number of storage circuits are coupled to comparators to store states of multiple bits, then the ADC can determine more bits, but the capacitive load increases which degrades operation speed and power efficiency
Solution Approach 1:
The patent divides the storage circuits into two separate sets: a first set coupled to the first comparator and a second set coupled to the second comparator. This segmentation reduces the capacitive load on each individual comparator while maintaining the ability to store states for multiple bits, thus resolving the contradiction between measurement precision and operation speed.
2Measurement precision
If a large number of storage circuits are coupled to comparators to store states of multiple bits, then the ADC can determine more bits, but the power consumption increases due to higher capacitive load
Solution Approach 1:
By segmenting the storage circuits into two separate sets coupled to different comparators, the patent reduces the power consumption of each comparator. The first comparator handles first subset bits with its dedicated first set of storage circuits, while the second comparator handles second subset bits with its dedicated second set of storage circuits, improving overall power efficiency.
3Device complexity
If a single comparator is used to determine all bits, then the device complexity is reduced, but the detection speed and sensitivity cannot be optimized for different bit subsets
Solution Approach 1:
The patent applies local quality by assigning different characteristics to different comparators: the first comparator is optimized for faster detection speed to determine first subset bits, while the second comparator is optimized for higher sensitivity to determine second subset bits. This local optimization resolves the contradiction between device complexity and detection performance.
Data Source
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AI summary
Disclosed herein are related to systems and methods for a power efficient successive approximation analog to digital converter (SAR ADC). In one aspect, the SAR ADC includes a sample and digital to analog conversion (DAC) circuit to sample an input voltage. In one aspect, the SAR ADC includes a first comparator coupled to the DAC circuit, and a first set of storage circuits coupled between the first comparator and the DAC circuit. In one aspect, the SAR ADC includes a second comparator coupled to the DAC circuit, and a second set of storage circuits coupled between the second comparator and the DAC circuit. In one aspect, the SAR ADC includes a control circuit configured to select, for each of multiple bits corresponding to the input voltage, a corresponding comparator to determine a state of the each of the multiple bits during a corresponding time period.