Dual-Comparator Signal Rectification for Low-Phase-Shift Timing
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Solution Overview
Problem
Existing comparator circuits face issues with frequent amplitude transitions due to background noise, leading to spurious switches and phase shifts in signal processing, particularly when using a single comparator with hysteresis to compare analog signals with upper and lower threshold levels.
Innovation Solution
A signal rectification and timing circuit utilizing two comparators, each comparing the variable amplitude input signal with a separate upper and lower threshold, respectively, and generating digital output signals that are processed by a logic array to produce a digital level pulse output with minimal phase shift, eliminating the need for a feedback circuit and reducing propagation delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single comparator with hysteresis is used to eliminate bounce, then spurious transitions are reduced, but propagation delay increases causing phase shift
Solution Approach 1:
The patent divides the single comparator function into two separate comparators: one dedicated to detecting upper threshold crossings and another dedicated to detecting lower threshold crossings. Each comparator operates independently with its own hysteresis circuit, eliminating the sequential processing delay of feedback-based hysteresis while maintaining signal stability.
2Reliability
If feedback circuit is used to control bounce, then spurious switches are eliminated, but device complexity increases
Solution Approach 1:
The patent extracts and eliminates the feedback circuit from the system by using two independent comparators that directly compare the input signal against reference thresholds. This removes the complex feedback loop while maintaining bounce elimination through the independent operation of dual comparators with hysteresis.
3Measurement precision
If hysteresis is applied to eliminate bounce, then measurement precision is maintained, but propagation delay causes phase shift
Solution Approach 1:
The patent applies hysteresis in advance within each comparator's input stage, before the signal needs to be processed sequentially. By pre-configuring upper and lower threshold levels in each comparator and applying hysteresis locally, the system achieves accurate threshold detection without the propagation delay associated with feedback-based hysteresis switching.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively minimizes spurious transitions and phase errors, providing a precise digital output signal with reduced bounce and propagation delay, enhancing the accuracy and reliability of signal processing.
Implementation Method 1
Each comparator has a hysteresis circuit to prevent rapid fluctuation and bounce
Data Source
AI summary
A method and an associated apparatus for a signal rectification and timing circuit. A variable amplitude input signal is generated. An upper threshold level is determined and a lower threshold level is determined. The variable amplitude input signal and the upper threshold level are input into a first comparator. The variable amplitude input signal and the lower threshold level are input into a second comparator. A first digital output signal is generated in the first comparator using a hysteresis circuit and a second digital output signal is generated in the second comparator using a hysteresis circuit. The first digital output signal and the second digital output signal are input into a logic array. A digital level pulse output signal is generated in the logic array that has a digital transition where the variable amplitude input signal passed through a threshold level.