Dual-Comparator Circuit for Transient Threshold Voltage Offset
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Solution Overview
Problem
High-frequency operation of transistors in advanced CMOS technologies leads to transient variations in transistor parameters, causing threshold voltage instability and errors in comparators used in analog-to-digital converters, particularly due to charge trapping, self-heating, and floating body effects, which degrade the accuracy of mixed-signal circuits.
Innovation Solution
Implementing a dual-comparator circuit scheme where one comparator makes the initial decision and the second, with transistors held in a symmetric bias point, makes a subsequent decision closer to zero voltage crossing, reducing the impact of transient variations by exchanging stressed transistors and using switches to manage the input and output signals effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistors operate at high frequencies in advanced CMOS technologies, then productivity is improved, but transient variations in transistor parameters occur causing threshold voltage instability
Solution Approach 1:
The patent divides the comparator operation into multiple stages: a first input stage that makes an initial decision and a second input stage that makes a subsequent decision closer to zero voltage crossing. This segmentation allows the system to handle high-frequency operations while maintaining threshold stability by distributing the decision-making process across time and circuit stages.
Solution Approach 2:
The first input stage performs a preliminary decision before the second input stage makes the final comparison. This preliminary action prepares the circuit state and allows transient variations to settle before the critical threshold comparison occurs, thereby maintaining stability during high-frequency operation.
2Productivity
If a comparator is overdriven at its input to make decisions, then productivity is improved, but transient variations cause threshold offset voltage appearing at the input stage
Solution Approach 1:
The conversion process is segmented into multiple stages where the first input stage handles rough estimation and the second input stage performs precise comparison near zero voltage crossing. This segmentation allows overdriving for speed in the first stage while maintaining precision in the second stage.
Solution Approach 2:
The patent dynamically switches between different operating modes: the first input stage operates with larger voltage swings for faster conversion, while the second input stage operates near zero voltage crossing for higher precision. This dynamic adaptation resolves the contradiction between speed and accuracy.
3Stability of the object's composition
If transistors are held in symmetric bias point in the second comparator circuit, then threshold voltage stability is improved, but device complexity increases
Solution Approach 1:
The patent applies symmetric bias point holding only to the second input stage, not the entire comparator circuit. This selective application maintains threshold stability where needed while minimizing the impact on overall circuit complexity.
Solution Approach 2:
The symmetric bias point technique is applied locally to the second input stage transistors rather than uniformly across all transistors. This local quality approach improves threshold stability at the critical comparison point while avoiding unnecessary complexity in other parts of the circuit.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces threshold voltage variations and improves the accuracy of comparators by minimizing errors introduced by transient parameter changes, ensuring more precise conversions, especially in high-frequency operations.
Implementation Method 1
transient variations of transistor parameters (e.g. VT, μ . . . ) in advanced CMOS technologies are caused by effects such as charge trapping
Implementation Method 2
transient variations of transistor parameters (e.g. VT, μ . . . ) in advanced CMOS technologies are caused by effects such as charge trapping, self heating or floating body effects
Data Source
AI summary
This disclosure relates to permuting transistors to compensate for offsets generated by transient variations of the transistors' parameters.