Conductive Vias with Dual-Layer Conductivity for Memory Current Distribution
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In integrated circuitry, the challenge is to provide sufficient conductive contact area between closely packed circuit components, particularly where coupling is through substantially horizontal surfaces, as the vertical dimension increases and horizontal dimension decreases, leading to uneven current distribution during write operations in memory cells.
Innovation Solution
The formation of conductive vias with varying conductivities, where a first conductive material with lower conductivity is used to fill one via opening and a second conductive material with higher conductivity is used to fill another, creating vias with distinct conductance levels to evenly distribute current and reduce resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the vertical dimension of circuit components is increased to maintain conductive contact area, then electrical coupling between components is improved, but the horizontal dimension must be reduced which increases component density and fabrication complexity
Solution Approach 1:
The patent applies local quality by forming conductive vias with non-uniform cross-sectional areas along their vertical extent. Specifically, the via openings are configured to have different horizontal dimensions at different elevations, creating varying conductive contact areas at different levels. This allows optimization of electrical coupling at specific interfaces without uniformly increasing the vertical dimension of all components, thereby addressing the contradiction between reliable electrical coupling and fabrication complexity.
2Reliability
If conductive vias are made taller to provide sufficient conductive contact area, then electrical coupling between elevated components is improved, but resistance to current flow increases causing uneven current distribution
Solution Approach 1:
The patent implements local quality by creating conductive vias with non-uniform cross-sectional areas where the horizontal dimension varies at different elevations. This configuration provides larger conductive contact areas at specific interfaces to reduce contact resistance, while maintaining appropriate via dimensions elsewhere. The varying cross-sectional area compensates for the increased vertical path length, ensuring uniform current distribution across memory cells despite taller via structures.
Solution Approach 2:
The patent applies parameter changes by varying the horizontal dimension of via openings at different elevations rather than maintaining a uniform cross-sectional area. This parameter variation along the vertical axis allows optimization of electrical properties at different interfaces, reducing contact resistance where needed while controlling overall via resistance to maintain current distribution uniformity across the memory array.
3Manufacturing precision
If multiple conductive vias are provided to each access line and sense line, then current distribution is improved, but device complexity and fabrication difficulty increase
Solution Approach 1:
The patent applies local quality by implementing non-uniform cross-sectional areas within individual conductive vias rather than requiring multiple separate vias per line. The varying horizontal dimension at different elevations creates multiple effective conductive pathways within a single via structure, achieving improved current distribution while avoiding the fabrication complexity of forming and aligning multiple distinct via openings to each line.
Data Source
AI summary
A method of forming conductive vias comprises forming a first via opening and a second via opening within a substrate. First conductive material of a first conductivity is formed into the first and second via openings. The first conductive material lines sidewalls and a base of the second via opening to less-than-fill the second via opening. Second conductive material is formed into the second via opening over the first conductive material in the second via opening. The second conductive material is of a second conductivity that is greater than the first conductivity. All conductive material within the first via opening forms a first conductive via defining a first maximum conductance elevationally through the first conductive via and all conductive material within the second via opening forms a second conductive via defining a second maximum conductance elevationally through the second conductive via that is greater than said first maximum conductance. Integrated circuit structure comprising conductive vias independent of method of manufacture are disclosed.