Dual Contact Structure for Gate Last Process
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Solution Overview
Problem
The integration of a first contact structure in a gate last process for semiconductor devices is challenging due to issues such as void formation and erosion during chemical mechanical polishing (CMP) processes, which can lead to defective connections to doped regions and alignment problems in high and low pattern density regions.
Innovation Solution
A method for fabricating a semiconductor device with a dual first contact structure involves forming a first contact plug with a metal barrier layer, a dummy contact plug in low pattern density regions to prevent erosion, and a second contact plug coupled to the first, along with a dielectric barrier layer to ensure planarity and prevent metal residue issues, allowing for effective replacement of dummy poly gates with metal gates and subsequent CMP processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a gate last process is implemented to replace polysilicon gate with metal gate, then device performance is improved, but integration with first contact structure formation becomes problematic due to void formation and erosion during CMP processes
Solution Approach 1:
The first contact structure is divided into two distinct contact plugs: a first contact plug formed through the interlayer dielectric, and a second contact plug formed through a second interlayer dielectric. This segmentation allows each contact plug to be optimized independently for its specific function, preventing the void formation and erosion issues that occur when using a single contact structure in gate last processes.
Solution Approach 2:
The first contact plug is formed preliminarily before the metal gate is deposited. This preliminary action allows the first contact structure to be established while the dummy poly gate is still present, avoiding the erosion and void formation problems that occur when attempting to form contacts after metal gate deposition in gate last processes.
2Shape
If chemical mechanical polishing is used to planarize the surface after first contact formation, then surface planarity is improved, but erosion and void formation occur leading to defective connections
Solution Approach 1:
The solution introduces a vertical dimension by forming a second contact plug through a second interlayer dielectric that is deposited over the first interlayer dielectric. This multi-layer approach allows the CMP process to planarize each layer independently, maintaining surface planarity while preventing erosion and void formation from affecting connection integrity through the additional protective layer.
Solution Approach 2:
The second interlayer dielectric acts as a cushioning layer deposited beforehand to protect the first contact structure from erosion and void formation during subsequent CMP processes. This protective layer prevents defective connections while still allowing the necessary planarization to occur.
3Reliability
If dummy poly gate is removed and replaced with metal gate, then thermal and blocking properties are improved, but alignment problems occur in high and low pattern density regions
Solution Approach 1:
The patent applies different qualities to different regions by forming the first contact plug with specific dimensions and materials tailored to high pattern density regions, while the second contact plug is designed with different characteristics suitable for low pattern density regions. This local quality approach resolves alignment problems by optimizing each contact structure for its specific regional requirements while maintaining the improved thermal and blocking properties of the metal gate.
Data Source
AI summary
A method is provided that includes providing a substrate; forming a transistor in the substrate, the transistor having a dummy gate; forming a dielectric layer over the substrate and transistor; forming a contact feature in the dielectric layer; and after forming the contact feature, replacing the dummy gate of the transistor with a metal gate. An exemplary contact feature is a dual contact.


