Dual Control Gate Flash Memory Cell Arrays
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Solution Overview
Problem
The shrinking size of non-volatile memory cell arrays is limited by the thickness of floating gate dielectric, leading to increased coupling between gates and parasitic capacitances, which causes errors in programming and reading, especially in multi-state operations, and makes it difficult to reduce control gate voltages.
Innovation Solution
A dual control gate non-volatile memory structure is formed with conductive strips acting as floating gates and control gates, where the control gates are positioned between the floating gates to increase coupling area and reduce parasitic capacitances, allowing for lower control gate voltages and improved capacitive coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the size of memory cell arrays is shrunk, then storage capacity increases, but parasitic capacitances increase causing errors in programming and reading
Solution Approach 1:
The single control gate is segmented into two separate control gates (first and second control gates) positioned on opposite sides of the floating gate. This segmentation distributes the capacitive coupling function across multiple elements, reducing the parasitic capacitance impact on any single gate while maintaining or enhancing overall coupling efficiency to the floating gate.
Solution Approach 2:
The floating gate acts as an intermediary element between the two control gates and the charge storage region. By positioning control gates on both sides of the floating gate, the structure uses the floating gate as a mediating capacitor that couples the control signals from both gates to the charge storage region, thereby enhancing the effective coupling ratio while isolating the control gates from direct parasitic interactions.
2Use of energy by moving object
If control gate voltage is reduced, then power consumption decreases, but coupling ratio is insufficient to achieve lower voltages
Solution Approach 1:
The first and second control gates work together in combination to provide enhanced capacitive coupling to the floating gate. By merging the coupling effects of two control gates positioned on opposite sides, the structure achieves a higher effective coupling ratio than a single control gate could provide, enabling the system to operate at lower voltages with reduced power consumption.
Solution Approach 2:
The control gate structure transitions from a single-plane configuration to a three-dimensional arrangement with control gates positioned on opposite sides of the floating gate. This dimensional change increases the effective coupling area and improves the coupling ratio by utilizing spatial distribution, allowing lower operating voltages while maintaining reliable charge storage and retrieval.
3Volume of moving object
If floating gate dielectric thickness is reduced, then device size decreases, but coupling between gates increases causing errors
Solution Approach 1:
The structure employs asymmetric positioning of the first and second control gates on opposite sides of the floating gate, creating an balanced capacitive coupling configuration. This asymmetric arrangement around the floating gate allows for reduced dielectric thickness while maintaining proper coupling ratios, as the opposite-side positioning compensates for the reduced thickness by distributing the electric field more effectively.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the capacitive coupling ratio, reduces errors, and enables lower control gate voltages, facilitating the scaling of memory arrays without compromising data retention or increasing voltage requirements.
Implementation Method 1
The control gate lines are typically formed over the floating gates as a self-aligned stack, and are capacitively coupled with each other through an intermediate dielectric layer 19
Data Source
AI summary
Methods of fabricating a dual control gate non-volatile memory array are described. Parallel strips of floating gate material are formed over the substrate in a first direction but separated from it by a tunnel dielectric. In the gaps between these strips control gate material is formed forming a second set of parallel strips but insulated from both the adjacent floating gate stripes and the substrate. Both sets of strips are isolated in a second direction perpendicular to the first direction forming an array of individual floating gates and control gates. The control gates formed from an individual control gate strip are then interconnected by a conductive wordline such the potential on individual floating gates are controlled by the voltages on two adjacent wordlines. In other variations either the floating gates or the control gates may be recessed into the original substrate.