Dual Control Circuit Memory System for Single Channel Throughput
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Solution Overview
Problem
Memory systems with multiple channels face reduced operation speed when using only one channel, as other channels are not utilized, leading to slower data access and processing.
Innovation Solution
A memory system architecture that includes dual control circuits and flash translation layers connected through internal channels, allowing data to be alternately transmitted between control circuits and chip groups via a single host channel, enabling simultaneous data processing and caching across multiple chip groups.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple channels are provided in the memory system, then the storage capacity and data access capability are improved, but the operation speed deteriorates when only one channel is used
Solution Approach 1:
The memory system segments the control functions into multiple control circuit parts (first control circuit part, second control circuit part), each capable of independently managing memory chip groups. This segmentation allows the system to utilize multiple control circuits even when only one host channel is active, thereby maintaining high operation speed while preserving the capability for expanded storage capacity through additional channels.
2Productivity
If multiple channels are utilized for simultaneous access, then the data processing throughput is improved, but the system complexity increases
Solution Approach 1:
Each control circuit part is designed with multi-functionality, capable of both receiving data directly from the host channel and receiving data from buffers. The control circuits can operate independently or in coordination, allowing the system to achieve high data processing throughput through simultaneous access while managing complexity through standardized, versatile control units that can adapt to different operational modes.
Solution Approach 2:
Buffers are introduced as intermediary components between the host channel and control circuit parts. These buffers temporarily store data and enable decoupling of data transfer operations from processing operations, allowing the system to maintain high throughput without proportionally increasing control complexity. The buffers mediate data flow, enabling efficient coordination between multiple channels and control circuits.
Data Source
AI summary
A memory system includes a first control circuit part configured to communicate with a host through a first host channel, a second control circuit part configured to communicate with the host through a second host channel, a first chip group configured to communicate with the first control circuit part through a first internal channel, and a second chip group configured to communicate with the second control circuit part through a second internal channel, wherein the first control circuit part and the second control circuit part alternately receive a plurality of data inputted through one of the first and second host channels, which is selected during a single channel operation, and transmit the data to the first chip group and the second chip group.