Dual-Controller Cache Redundancy Using a Shared Memory Module
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Solution Overview
Problem
Existing storage apparatuses face issues with degraded reliability and availability when one of the controllers is blocked, leading to impaired data redundancy and performance degradation.
Innovation Solution
The storage apparatus is configured with a first and second controller, each with a memory, and a memory module connected to both controllers, allowing for the transfer and redundancy of cache data and control information to maintain operation even if one controller is blocked.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundancy is provided to the controller by placing data in both controllers' memories, then reliability is improved, but when one controller is blocked the availability is degraded due to impaired redundancy
Solution Approach 1:
A shared memory module is introduced as an intermediary between the two controllers. This memory module serves as a mediator that both controllers can access, allowing them to share cache data and maintain redundancy even when one controller is blocked. The shared memory module enables the non-blocked controller to access data that would otherwise be unavailable, thus maintaining availability while preserving redundancy.
Solution Approach 2:
The patent adds a new dimension to the storage architecture by introducing a shared memory module that exists outside the individual controller memory spaces. This creates a third dimension of data storage that both controllers can access, transforming the traditional two-controller redundancy model into a more flexible three-component system that maintains redundancy without compromising availability during controller failures.
2Speed
If data is placed in high-speed memory such as DRAM to enhance performance, then access speed is improved, but when one controller is blocked the performance degrades due to loss of redundancy
Solution Approach 1:
The shared memory module acts as an intermediary that preserves high-speed data access capability even when one controller is blocked. By storing cache data in the shared memory module, the system maintains fast access paths through the non-blocked controller, preventing performance degradation while preserving the benefits of high-speed memory access.
Solution Approach 2:
The patent changes the storage parameter by introducing a shared memory module that can be dynamically accessed by either controller. This parameter change allows the system to maintain high-speed access characteristics under normal operation and gracefully degrade to a single-controller mode during failures, preserving performance while adapting to changing system states.
3Ease of operation
If uniform addressing is applied across the entire memory sharing resource pool, then addressing simplicity is improved, but a mechanism to ensure reliability and availability during controller blockage is not provided
Solution Approach 1:
The patent segments the memory addressing space into controller-specific portions and a shared portion. Each controller has its own address space for exclusive use, while the shared memory module provides a separate addressable space that both controllers can access. This segmentation maintains addressing simplicity within each segment while enabling reliable operation during controller failures through the shared segment.
Data Source
AI summary
A storage apparatus includes a first controller having a first memory, a second controller having a second memory, and a memory module having a third memory. The first memory stores drive control information including a correspondence between a logical address and a physical address, first cache data in a data input-output (I/O) process, and first cache control information including a correspondence between a logical address and a cache address of the first cache data. The second memory stores drive control information, second cache data in the data I/O process, and second cache control information including a correspondence between a logical address and a cache address of the second cache data. The third memory stores first cache data provided with redundancy and second cache data provided with redundancy.