Dual Conversion Gain Comparator for High Dynamic Range ADC Readout
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Solution Overview
Problem
Existing image sensors with dual conversion gain for high dynamic range operation face challenges in managing reset levels between high and low conversion gain modes, leading to increased comparator area and parasitic capacitance effects that impact frame rate.
Innovation Solution
A two-input dual-stage comparator design is implemented, with cascode devices arranged adjacent to a current mirror and second stage, reducing parasitic capacitance and enabling faster ADC operations by selectively coupling input stages and control signals to manage conversion gain modes effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If two comparators are used to compensate for reset level differences in high and low conversion gain modes, then measurement precision is improved, but device complexity and area increase
Solution Approach 1:
The comparator is designed with dynamic reconfiguration capability, allowing a single comparator to switch between handling high conversion gain and low conversion gain modes. The input stage can be selectively coupled to different pixel groups depending on the conversion gain mode, enabling one comparator to replace what would traditionally require two comparators, thus reducing device complexity while maintaining measurement precision
Solution Approach 2:
The comparator is designed to perform multiple functions by serving both high conversion gain and low conversion gain modes. The same comparator circuitry is used for both gain modes through selective coupling of input stages, making the comparator universal and eliminating the need for separate comparators for each mode
2Measurement precision
If two sets of input stages are used in the comparator, then measurement precision is improved, but parasitic capacitance increases affecting frame rate
Solution Approach 1:
The input stages are dynamically selected based on the conversion gain mode rather than being permanently present. Switching mechanisms allow only the required input stage to be active at any given time, reducing the total parasitic capacitance compared to having two permanent input stages, thereby improving frame rate while maintaining the ability to compensate for reset level differences
3Productivity
If parasitic capacitance is reduced through layout optimization, then frame rate is improved, but manufacturing precision requirements increase
Solution Approach 1:
The comparator is divided into distinct functional modules (input stages, switching mechanisms, processing stages) that can be independently optimized. This segmentation allows for systematic layout optimization to minimize parasitic capacitance between modules while maintaining manufacturability, as each module can be designed and fabricated with standard precision requirements rather than requiring ultra-precise overall layout
Data Source
AI summary
A method includes coupling a low gain input of a dual stage comparator to establish a low conversion gain mode. An analog-to-digital (ADC) operation is performed to determine a low gain reset voltage. A low gain input is decoupled in response to a DCG control signal. A high gain input is coupled to establish a high conversion gain mode in response to the DCG control signal. The ADC operation is performed with the high gain input to determine a high gain reset voltage. The ADC operation is performed with the high gain input to determine a high gain signal voltage. The high gain input is decoupled in response to a DCG control signal transition. The low gain input is recoupled in response to the DCG control signal, and the ADC operation is performed with the low gain input to determine a low gain signal voltage.